LT1016IS8 datasheet(3/20 Pages) LINER

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LT1016

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: Input offset voltage is defined as the average of the two voltages

measured by forcing first one output, then the other to 1.4V. Input offset

current is defined in the same way.

Note 3: Input bias current (IB) is defined as the average of the two input

currents.

Note 4: tPD and

DtPD cannot be measured in automatic handling

equipment with low values of overdrive. The LT1016 is sample tested with

a 1V step and 500mV overdrive. Correlation tests have shown that tPD and

The

● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25

∞C. V+ = 5V, V– = 5V, VOUT (Q) = 1.4V, VLATCH = 0V, unless otherwise noted.

LT1016C/I

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VOS

Input Offset Voltage

£ 100W (Note 2)

1.0

±3mV

●

3.5

DVOS

Input Offset Voltage Drift

●

mV/∞C

IOS

Input Offset Current

(Note 2)

0.3

1.0

●

0.3

1.3

Input Bias Current

(Note 3)

●

Input Voltage Range

(Note 6)

●

–3.75

3.5

Single 5V Supply

●

1.25

3.5

CMRR

Common Mode Rejection

–3.75V

£ VCM £ 3.5V

●

PSRR

Supply Voltage Rejection

Positive Supply 4.6V

£ V+ £ 5.4V

●

LT1016C

Positive Supply 4.6V

£ V+ £ 5.4V

●

LT1016I

Negative Supply 2V

£ V– £ 7V

●

100

Small-Signal Voltage Gain

£ VOUT £ 2V

1400

3000

V/V

VOH

Output High Voltage

V+

≥ 4.6V

IOUT =1mA

●

2.7

3.4

IOUT = 10mA

●

2.4

3.0

VOL

Output Low Voltage

ISINK = 4mA

●

0.3

0.5

ISINK = 10mA

0.4

I+

Positive Supply Current

●

I–

Negative Supply Current

●

VIH

LATCH Pin Hi Input Voltage

●

2.0

VIL

LATCH Pin Lo Input Voltage

●

0.8

IIL

LATCH Pin Current

VLATCH = 0V

●

500

tPD

Propagation Delay (Note 4)

DVIN = 100mV, OD = 5mV

●

DVIN = 100mV, OD = 20mV

●

DtPD

Differential Propagation

(Note 4)

DVIN = 100mV,

Delay

OD = 5mV

Latch Setup Time

2ns

DtPD limits shown can be guaranteed with this test if additional DC tests

are performed to guarantee that all internal bias conditions are correct. For

low overdrive conditions VOS is added to overdrive. Differential

propogation delay is defined as:

DtPD = tPDLH – tPDHL

Note 5: Electrical specifications apply only up to 5.4V.

Note 6: Input voltage range is guaranteed in part by CMRR testing and in

part by design and characterization. See text for discussion of input

voltage range for supplies other than

±5V or 5V.

Note 7: This parameter is guaranteed to meet specified performance

through design and characterization. It has not been tested.

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