1.8V to 3.3V PicoPLL

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 2

KEY PROGRAMMING PARAMETERS

CLK

Output Frequency

Output Drive Strength

Programmable

Input/Output

Where M = 11 bit

R = 8 bit

P = 5 bit

Three optional drive strengths to

choose from:

• Low: 4mA

• Std: 8mA (default)

• High: 16mA

One output pin can be configured

as:

• OE - input

• PDB - input

• FSEL – input

PACKAGE PIN ASSIGNMENT

Pin Assignment

Name

DFN

Pin#

SOT

Pin #

Type

Description

CLK1

2

1

O

Programmable Clock Output

GND

3

2

P

GND connection

FIN

1

3

I

Reference input pin

OE,

PDB,

FSEL

6

4

I

This programmable I/O pin can be configured as an Output Enable (OE)

input, Power Down (PDB) input or Frequency Switching (FSEL) input. This

pin has an internal 60K

pull up resistor.

The OE and PDB features can be programmed to allow the output to float

(Hi Z), or to operate in the ‘Active low’ mode.

State

OE

PDB

FSEL

0

Disable CLK

Power Down Mode

Frequency ‘2’

1 (default)

Normal mode

Normal mode

Frequency ‘1’

VDD

5

5

P

VDD connection

CLK0

4

6

O

Programmable Clock Output

OE AND PDB FUNCTION DESCRIPTION

OE

PDB

Osc.

PLL

CLK0

CLK1

1

N/A

On

On

On

On

0

N/A

On

Off

HiZ or Active Low

On

N/A

1

On

On

On

On

N/A

0

Off

Off

HiZ or Active Low

HiZ or Active Low

Note: HiZ or Active Low states are programmable functions and will be set per request.