1.8V to 3.3V PicoPLL

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 1

FEATURES

• Advanced One Time Programmable (OTP) PLL design

• Programmable PLL or direct oscillation operation

• Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)

• Output Frequency up to

o

65MHz @ 1.8V operation

o

9/MHz @ 2.5V operation

o

125MHz @ 3.3V operation

• Reference Input Frequency: 1MHz to 200MHz

• Accepts >0.1V reference signal input voltage

• Low current consumption, <10 A when PDB is

activated

• One programmable I/O pin can be configured as

Output Enable (OE), Frequency Switching

(FSEL), or Power Down (PDB) input.

• Disabled outputs programmable as HiZ or Active Low.

• Single 1.8V, 2.5V, or 3.3V ± 10% power supply

• Operating temperature range from 0°C to 70°C

Compliant packages

DESCRIPTION

The PL611s-27 is a general purpose frequency

synthesizer and a member of PhaseLink’s PicoPLL

product family. Designed to fit in a small 6-pin DFN,

or 6-pin SOT package for high performance

applications, the PL611s-27 offers very low phase

noise, jitter, and power consumption, while offering 2

clock outputs. The Frequency Switching (FSEL)

capability of PL611s-27 allows for programming two

sets of frequencies, while the power down feature of

PL611s-27, when activated, allows the IC to

consume less than 10 A of power. PL611s-27’s

programming flexibility allows generating any output

using a Reference input signal.

PACKAGE PIN CONFIGURATION

BLOCK DIAGRAM

Phase

Detector

Charge

Pump

Loop

Filter

VCO

FIN

R-counter

(8-Bit)

Fvco=Fref* (2 * M /R)

CLK1

CLK0

Programming

Logic

OE, PDB,

FSEL

(11-Bit)

(5-Bit)

M-counter

P-counter

Programmable Function

1

2

3

4

5

6

CLK1

GND

FIN

VDD

OE, PDB, FSEL

CLK0

DFN

DFN

DFN

DFN----6

6

6

6L

L

L

L

((((2

2

2

2....0

0

0

0mmx

mmx

mmx

mmx1

1

1

1....3

3

3

3mmx

mmx

mmx

mmx0

0

0

0....6

6

6

6mm

mm

mm

mm))))

SOT

SOT

SOT

SOT23

23

23

23----6

6

6

6L

L

L

L

((((3

3

3

3....0

0

0

0mmx

mmx

mmx

mmx3

3

3

3....0

0

0

0mmx

mmx

mmx

mmx1

1

1

1....35

35

35

35mm

mm

mm

mm))))

FIN

CLK1

GND

OE, PDB, FSEL

VDD

CLK0

1

2

3

6

5

4