PLL650-02

Low EMI Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

XIN

2

I

XOUT/50MHz_OE

3

B

Crystal connection pin. At power-up, this pin latches 50MHz_OE (output

enable selector for all 50MHz outputs. Disabled when 50MHz_OE is logical

zero. Has 120k

Ω internal pull up resistor.

50MHz/FS(0:2)

50MHz/SS0

6,8,9,11

B

Bi-directional pins. 50MHz outputs. These pins latch FS(0:2) and SS0 at

power-up. 60k

Ω internal pull up resistors on pins 6 and 8.

FS3

10

I

Tri-level input pin. FS3 input put.

25MHz/125MHz

13,15

O

25MHz (reference) or 125MHz outputs. Can be disabled with FS3 = 1.

SDRAMx2

18,20

O

SDRAM outputs with double drive strength determined by FS(0:1) value.

25MHz/100MHz

22

O

25MHz (reference) or 100MHz output. Can be disabled with FS2 = M.

VDD

1,5,12,

16,17,23,24

P

3.3V power supply.

GND

4,7,14,19,21

P

Ground.

SPREAD SPECTRUM SELECTION TABLE

SS0

SST modulation

0

±0.75% center

M

OFF

1

±0.5% center

FUNCTIONAL DESCRIPTION

Selectable spread spectrum and output frequencies

The PLL650-02 provides selectable spread spectrum modulation and selectable output frequencies. Selection is made by

connecting specific pins to a logical “zero” or “one”, or by leaving them not connected (tri-level inputs or internal pull-up)

according to the frequency and spread spectrum selection tables shown on pages 1 and 2 respectively.

In order to reduce pin usage, the PLL650-02 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0

(Connect to GND), 1 (Connect to VDD), M (Do not connect). Thus, unlike the two-level selection pins, the tri-level input pins are

in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to

GND. Likewise, in order to connect to a logical “one” the pin must be connected to VDD.

Pin 3 (XOUT/50MHz_OE) is a bi-directional pin used to disable the 50MHz output pins. Pin 6 (FS0) and pin 8 (FS1) are bi-

directional pins used to select the SDRAM output frequency upon power-up. Pin 9 (FS2) and pin 11 (FS3) are tri-level bi-

directional pins used to select the output frequency of pins 13, 15 and 22, as shown in the frequency table on page 1. After the

input signals have been latched, pins 6, 8, 9, and 11 serve as 50 MHz frequency outputs.