PLL650-02

Low EMI Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

• Advanced, low power, sub-micron CMOS processes.

• 25MHz fundamental crystal or clock input.

• 4 outputs at 50MHz, 2 outputs selectable at 25MHz or

125MHz, 1 output selectable at 25MHz or 100MHz.

• 2 SDRAM selectable frequencies of 66.6, 75, 83.3,

100MHz (Double Drive Strength).

• All non SDRAM outputs can be disabled (tri-state)

• Spread spectrum technology selectable for EMI

reduction from

±0.5%, ±0.75% for SDRAM and 100MHz

output.

• Zero PPM synthesis error in all clocks.

• Ideal for Network switches.

• 3.3V operation.

•

DESCRIPTIONS

The PLL 650-02 is a low cost, low jitter, and high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, the chip

accepts 25 MHz crystal, and produces multiple output

clocks for networking chips, PCI devices, SDRAM, and

ASICs, with double drive strength for its SDRAM outputs.

PIN CONFIGURATION

FREQUENCY TABLE

FS1

FS0

SDRAM

FS3

Pin 13, 15

FS2

Pin 22

0

0

0

Disable

0

25MHz

0

1

M

125MHz

M

Disable

1

0

1

25MHz

1

1

1

FS(2:3): Tri-level inputs.

SST: SST modulation applied (see selection table)

BLOCK DIAGRAM

XTAL

OSC

50MHz

(can be disabled)

XIN

XOUT

25MHz/125MHz

(can be disabled)

SDRAM (66.6, 75, 83.3, 100MHz)

25MHz/100MHz

(can be disabled)

Control

Logic

FS (0:3)

4

2

2

1

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

VDD

50MHz/FS1*^

GND

50MHz/FS0*^

VDD

GND

XOUT/50MHz_OE*^

XIN

VDD

VDD

VDD

25MHz/125MHz

GND

25MHz/125MHz

VDD

VDD

25MHz/100MHz

GND

SDRAMx2

GND

SDRAMx2

resistor. *: Bi-directional pin (input value is latched upon power-up).