5.9

Settling time

Settling time in an application can be defined as the amount of time between the input changes and the output

reaching its final value. It is usually defined with a given tolerance, so the output stability is reached when the

output stays within the given range around the final value. In figures 36 and 37, the settling time is measured in an

inverting configuration, using the so-called “false summing node” circuit.

Figure 50. Settling time measurement configuration

This circuit is used with a step input voltage from a positive or negative value to 0 V. The measurement point

being (VIN - VOUT)/2, and VOUT being in an ideal circuit equal to -VIN, the measurement point gives half of the

error on VOUT, comparatively to VIN. This error is compared to the tolerance, 0.1% or 0.01% for this circuit, to

deduce the settling time. This characteristic is particularly useful when driving an ADC. It is related to the slew

rate, GBP, and stability of the circuit. It also varies with the circuit gain, the circuit load, and the input voltage step

value. However, computing the value of the settling time in a given configuration is not straightforward. The

macromodel can give a good estimation, but prototyping can be necessary for fine circuit optimization.

5.10

PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power

supply. The power and ground traces are critical as they must provide adequate energy and grounding for all

circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic

inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that

connects the bottom and top layer ground planes together in many locations is often used. The copper traces that

connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

5.11

Macromodel

Accurate macromodels of the TSB952 device are available on the STMicroelectronics website at: www.st.com

and in the STMicroelectronics simulation software eDSim. These models are a trade-off between accuracy and

complexity (that is, time simulation) of the TSB952 operational amplifier. They emulate the nominal performance

of a typical device within the specified operating conditions mentioned in the datasheet. They also help to validate

a design approach and to select the right operational amplifier, but they do not replace on-board measurements.

TSB952

Application information

DS14576 - Rev 1

page 23/36