MPQ1925

– 100V, 4A, HIGH-FREQUENCY, HALF-BRIDGE GATE DRIVER

MPQ1925 Rev. 1.0

MonolithicPower.com

12

3/8/2022

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2022 MPS. All Rights Reserved.

PCB Layout Guidelines

Proper PCB layout is critical for the optimal

performance of the HS-FET and LS-FET gate

drivers.

The

MPQ1925

is

designed

to

accommodate negative undershoot; however,

excessive undershoot can lead to unpredictable

operation or damage to the IC. For the best

results, refer to Figure 4 and follow the

guidelines below:

1. Make the connection between the HS-FET

source and the LS-FET drain as direct as

possible to avoid a negative undershoot on

the phase node due to parasitic inductance.

2. Use surface-mount N-channel MOSFETs

that allow for a very short connection

between the HS-FETs and LS-FETs.

3. Place the bootstrap capacitor (C3) and

supply bypass capacitor (C2) as close as

possible to the IC.

4. Use multiple vias to connect the ground side

of these capacitors, which are connected to

a solid ground plane, to both the GND pin

and exposed pad.

5. Keep the high-current ground path between

the input supply, input bulk capacitor (C6),

and the MOSFETs away from the IC.

Figure 4: Recommended PCB Layout