24C01SC/24C02SC

DS21170E-page 4

 2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 24C01SC/02SC supports a bidirectional two-wire

bus and data transmission protocol. A device that

sends data onto the bus is defined as transmitter, and

a device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and

generates the Start and Stop conditions, while the

24C01SC/02SC works as slave. Both master and slave

can operate as transmitter or receiver, but the master

device determines which mode is activated.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited, although only the last 16 will be

stored when doing a write operation. When an

overwrite does occur, it will replace data in a first in first

out fashion.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse.

Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an Acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line high to enable

the master to generate the Stop condition.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note:

The 24C01SC/02SC does not generate

any Acknowledge bits if an internal

programming cycle is in progress.

SCL

SDA

(A)

(B)

(D)

(D)

(C)

(A)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition