 2004 Microchip Technology Inc.

DS21226E-page 13

24LCS61/24LCS62

8.0

READ OPERATIONS

Read operations are initiated in a similar way as the

write operations. There are three basic types of read

operations: current address read, random read, and

sequential read.

8.1

Current Address Read

The 24LCS61/62 contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous read access was to address n, the next

current address read operation would access data from

address n + 1. Upon receipt of the correct control byte

and ID byte, the 24LCS61/62 issues an acknowledge

and transmits the eight bit data word. The master will

not acknowledge the transfer but does generate a Stop

condition

and

the

24LCS61/62

discontinues

transmission (Figure 8-1).

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24LCS61/62 as part of a write operation.

After the ID byte and word address are sent, the master

generates a Start condition following the acknowledge.

This terminates the write operation, but not before the

internal address pointer is set. Then the master sends

the control byte and ID byte for a Read command. The

24LCS61/62 will then issue an acknowledge and

transmits the eight bit data word. The master will not

acknowledge the transfer but does generate a Stop

condition

and

the

24LCS61/62

discontinues

transmission (Figure 8-2).

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24LCS61/62 trans-

mits the first data byte, the master issues an acknowl-

edge as opposed to a Stop condition in a random

read. This directs the 24LCS61/62 to transmit the next

sequentially addressed 8-bit word (Figure 8-3).

To provide sequential reads the 24LCS61/62 contains

an internal address pointer which is incremented by

one at the completion of each operation. This address

pointer allows the entire memory contents to be serially

read during one operation. The internal address pointer

will

automatically

roll

over

from

address

7Fh

(24LCS51) or FFh (24LCS62) to address 00h.

FIGURE 8-1:

CURRENT ADDRESS READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

P

S

S

T

O

P

CONTROL

BYTE

S

T

A

R

T

DATA

A

C

K

A

C

K

DEVICE

ID BYTE

N

O

A

C

K

1

0

10 O 00 1

E

OE Bit = EDS Pin Output Enable; see Section 9.0 “External Device Select (EDS) Pin and Output Enable (OE) Bit”