TDA8366H datasheet(21/48 Pages) PHILIPS

21 / 48 page

January 1995

Philips Semiconductors

Objective speciﬁcation

I2C-bus controlled PAL/NTSC TV

processor

TDA8366

LUMINANCE INPUTS AND OUTPUTS (PINS 25 AND 26)

V26(p-p)

output signal amplitude

(peak-to-peak value)

top sync-white

−

0.45

0.63

VTS

top sync level

−

2.5

−

output impedance

−

250

−Ω

V25(p-p)

input signal amplitude

(peak-to-peak value)

−

0.45

−

Iclamp

clamp current

during burst key pulse

−

200

−µA

input current

no clamp

−−

0.5

µA

Chrominance ﬁlters

CHROMINANCE TRAP CIRCUIT

ftrap

trap frequency

−

fosc

−

MHz

trap quality factor

note 16

−

colour subcarrier rejection

−−

CHROMINANCE BANDPASS CIRCUIT

centre frequency

−

fosc

−

MHz

QBP

bandpass quality factor

−

Delay line and peaking circuit

Y DELAY LINE

delay time

note 6

−

480

−

td1

tuning range delay time

8 steps

−160

−

+160

bandwidth of internal delay line

note 6

−−

MHz

PEAKING CONTROL; note 17

fc(p)

peaking centre frequency

−

MHz

width of preshoot or overshoot

note 2

−

160

−

overshoot

positive

−

negative

−

peaking control curve

16 steps

see Fig.5

CORING STAGE

coring range

−

IRE

wave gain

−

1.8

−

Horizontal synchronization circuits

SYNC VIDEO INPUT (PINS 9, 11 AND 15)

V9,11,15

sync pulse amplitude

note 2

300

−

SLHS

slicing level for horizontal sync

note 18

−

SLVS

slicing level for vertical sync

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

negative half wave gain

positive half wave gain

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