ST8024

Electrical characteristics

13/30

Note:

1

All parameters remain within limits but are tested only statistically for the temperature

at the moment of measurement.

2

multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Figure 10.).

3

Permitted capacitor values are 100 + 100 nF, or 220 nF.

4

Transition time and duty factor definitions are shown in Figure 3.;

5

Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2

functions see Table 19.

6Pin PRES is active LOW; pin PRES is active HIGH see Figure 8. and Figure 9.; PRES has

present if at least one of the inputs PRES or PRES is active.

Figure 3.

Definition of output and input transition times

Table 19.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Activation time

(See

Figure 5.)180

220

µs

Deactivation time

(See

Figure 7.)60

80

100

µs

Start of the windows for sending

CLK to card

(See

Figure 6.)130

µs

End of the windows for sending

CLK to card

(See

Figure 6.)140

µs

Debounce time pins PRES and

PRES

(See

Figure 8.)140

µs