ST8024CDR datasheet(19/30 Pages) STMICROELECTRONICS

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ST8024

Functional description

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5.7

Active mode

When the activation sequence is completed, the ST8024 will be in its active mode. Data are

exchanged between the card and the microcontroller via the I/O lines.

The ST8024 is designed for cards without VPP (the voltage required to program or erase the

internal non-volatile memory).

5.8

Deactivation sequence

When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit

then executes an automatic deactivation sequence by counting the sequencer back and

finishing in the inactive mode (see

Figure 7.):

1. RST goes LOW (t10).

2. CLK is held LOW (t12 = t10 + 0.5 x T) where T is 64 times the period of the internal

oscillator (approximately 25 µs).

3. I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T).

4. VCC starts to fall towards zero (t14 = t10 + 1.5 x T).

5. The deactivation sequence is complete at tde, when VCC reaches its inactive state.

6. VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND;

I/OUC, AUX1UC and AUX2UC remain at VDD (pulled-up via a 11 kΩ resistor).

7. The internal oscillator returns to its lower frequency.

Figure 7.

Deactivation sequence

5.9

VCC Generator

The VCC generator has a capacity to supply up to 80 mA continuously at 5V and 65 mA at

3V. An internal overload detector operates at approximately 120 mA. Current samples to the

detector are internally filtered, allowing spurious current pulses up to 200 mA with a duration

in the order of µs to be drawn by the card without causing deactivation. The average current

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