AD8123

Rev. 0 | Page 14 of 16

POWER SUPPLY FILTERING

External power supply filtering between the system power

supplies and the AD8123 is required in most applications to

prevent supply noise from contaminating the received signal as

well as to prevent unwanted feedback through the supplies that

could cause instability. Figure 29 shows that the AD8123 power

supply rejection decreases with increasing frequency. These

plots are for the lowest control settings and shift upward as the

peaking is increased.

–60

–50

–40

–30

–20

–10

0

10

+PSRR

–PSRR

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 29. AD8123 PSRR vs. Frequency

A suitable filter that uses a surface-mount ferrite bead is shown

in Figure 30, and its frequency response is shown in Figure 31.

Because the frequency response was taken using a 50 Ω network

analyzer and with only one 0.1 μF capacitor on the AD8123

side, the actual amount of rejection provided by the filter in a

real-world application will be different from that shown in

Figure 31. The general shape of the rejection curve, however,

will match Figure 31, providing substantially increased overall

PSRR from approximately 5 MHz to 500 MHz, where it is most

needed. One filter is required on each of the two supplies (not one

filter per supply pin).

FAIR-RITE

2743021447

*ALL AD8123 SUPPLY PINS ARE INDIVIDUALLY

DECOUPLED WITH A 0.1µF CAPACITOR.

0.1µF

4700pF

4700pF

SYSTEM

SUPPLY

TO AD8123*

Figure 30. Power Supply Filter

–120

–100

–80

–60

–40

–20

0

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 31. Power Supply Filter Frequency Response in a 50 Ω System

LAYOUT AND POWER SUPPLY DECOUPLING

CONSIDERATIONS

Standard high speed PCB layout practices should be adhered

to when designing with the AD8123. A solid ground plane is

required and controlled impedance traces should be used when

interconnecting the high speed signals. Source termination

resistors on all of the outputs must be placed as close as possible

to the output pins.

The exposed paddle on the underside of the AD8123 must be

connected to a pad that connects to at least one PCB plane.

Several thermal vias should be used to make the connection

between the pad and the plane(s).

High quality 0.1 μF power supply decoupling capacitors should

be placed as close as possible to all of the supply pins. Small

surface-mount ceramic capacitors should be used for these, and

tantalum capacitors are recommended for bulk supply decoupling.

INPUT COMMON-MODE RANGE

Most applications that use the AD8123 as a receiver use a driver

(such as one from the AD8146/AD8147/AD8148 family, the

AD8133, or the AD8134) powered from ±5 V supplies. This

places the common-mode voltage on the line nominally at 0 V

relative to the ground potential at the driver and provides

optimum immunity from any common-mode anomalies picked

up along the cable (including ground shifts between the driver

and receiver ends). In many of these applications, the AD8123

input voltage range of typically ±3.0 V is sufficient. If wider

input range is required, the AD8143 triple receiver (input

common-mode range equals ±10.5 V on ±12 V supplies) may be

placed in front of the AD8123. Figure 32 illustrates how this is done

for one channel.