M95128-R datasheet(22/41 Pages) STMICROELECTRONICS

22 / 41 page

Instructions

M95128, M95128-W, M95128-R

22/41

Figure 11.

Page Write (WRITE) sequence

The most significant address bits (b15, b14) are Don’t Care.

5.6.1

ECC (Error Correction Code) and Write cycling

The M95128 (5V version, processed in F6DP26%, identified with letter "V") offers an ECC

(Error Correction Code) logic which compares each 4-Byte packet with its associated ECC

Word (6 EEPROM bits). As a result, if a single bit out of 4 Bytes of data happens to be

erroneous during a Read operation, the ECC detects it and replaces it by the correct value.

The read reliability is therefore much improved by the use of this feature.

Note however that even though a single Byte has to be written, 4 Bytes are internally

modified (plus the ECC Word), that is, the addressed Byte is cycled together with the three

other Bytes making up the packet. It is therefore recommended to Write by packets of 4

Bytes in order to benefit from the larger amount of Write cycles.

The maximum number of Write cycles for the M95128 device (5V version, processed in

F6DP26%, identified with letter "V") is qualified as 100,000 Write cycles, using a cycling

routine that writes to the device Page by Page (that is, by multiples of 4-Byte packets).

The M95128-W and M95128-R devices (2.5V and 1.8V versions, processed in F6DP36%

and identified with the letter "A") do not offer the ECC logic and are qualified for a maximum

number of 100,000 Write cycles.

AI01796D

35 36 37 38 39 40 41 42

44 45 46 47

3456789 10

20 21 22 23 24 25 26 27

14 13

3210

28 29 30

Instruction

16-Bit Address

765432

Data Byte 1

765432

Data Byte 2

765432

Data Byte 3

65432

Data Byte N

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