M95128-R datasheet(40/41 Pages) STMICROELECTRONICS

40 / 41 page

Revision history

M95128, M95128-W, M95128-R

40/41

13-Apr-2006

New M95128 datasheet extracted from the M95128/256 datasheet. Order

of sections modified.

ECC (Error Correction Code) and Write cycling paragraph added.

Section 3.7: Supply voltage (VCC) added and information removed below

Section 4: Operating features.

Power up state removed below Section 6: Delivery state.

Figure 13: SPI modes supported modified and Note 2 added.

ICC1 specified over the whole VCC range and ICC0 added to Table 13,

Table 14 and Table 15.

ICC specified over the whole VCC range in Table 13.

tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively.

Figure 16: Hold timing modified.

Process letter and Note 1 added to Table 22: Ordering information

scheme.

“AC Characteristics (M95128, Device Grade 6)” Table (for 10MHz

frequency) removed.

Note 1 removed from Table 19: AC characteristics (M95128-R).

TA added to Table 6: Absolute maximum ratings.

PDIP8 (BN) and SO8 wide (MW) packages removed. M95128-W and

M95128-R are no longer under development.

Test conditions changed for VOL and VOH in Section Table 14.: DC

characteristics (M95128-W, Device Grade 3).

27-Jun-2006

Figure 12: Bus master and memory devices on the SPI bus modified.

SO8N package specifications updated (see Table 20 and Figure 18).

V Process specified and A Process replaced by P in Table 22: Ordering

information scheme.

Table 23.

Document revision history (continued)

Date

Revision

Changes

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