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AD9912A/PCBZ 数据表(PDF) 29 Page - Analog Devices |
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AD9912A/PCBZ 数据表(HTML) 29 Page - Analog Devices |
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29 / 38 page ![]() Data Sheet AD9912 SERIAL CONTROL PORT analog.com Rev. G | 29 of 38 Table 11. Definitions of Terms Used in Serial Control Port Timing Diagrams Parameter Description tCLK Period of SCLK tDV Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO) tDS Setup time between data and rising edge of SCLK tDH Hold time between data and rising edge of SCLK tS Setup time between CSB and SCLK tH Hold time between CSB and SCLK tHI Minimum period that SCLK should be in a logic high state tLO Minimum period that SCLK should be in a logic low state |
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