AD9912ASLASHPCBZ datasheet(19/38 Pages) AD

19 / 38 page

Data Sheet

AD9912

THEORY OF OPERATION

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Rev. G | 19 of 38

SYSCLK PLL Doubler

The SYSCLK PLL multiplier path offers an optional SYSCLK PLL

doubler. This block comes before the SYSCLK PLL multiplier and

acts as a frequency doubler by generating a pulse on each edge of

the SYSCLK input signal. The SYSCLK PLL multiplier locks to the

falling edges of this regenerated signal.

The impetus for doubling the frequency at the input of the SYSCLK

PLL multiplier is that an improvement in overall phase noise per-

formance can be realized. The main drawback is that the doubler

output is not a rectangular pulse with a constant duty cycle even

for a perfectly symmetric SYSCLK input signal. This results in a

subharmonic appearing at the same frequency as the SYSCLK

input signal, and the magnitude of the subharmonic can be quite

large. When employing the doubler, care must be taken to ensure

that the loop bandwidth of the SYSCLK PLL multiplier adequately

suppresses the subharmonic.

The benefit offered by the doubler depends on the magnitude of

the subharmonic, the loop bandwidth of the SYSCLK PLL multiplier,

and the overall phase noise requirements of the specific applica-

tion. In many applications, the AD9912 clock output is applied to the

input of another PLL, and the subharmonic is often suppressed by

the relatively narrow bandwidth of the downstream PLL.

Note that generally, the benefits of the SYSCLK PLL doubler are

realized for SYSCLK input frequencies of 25 MHz and above.

Figure 44. System Clock Generator Block Diagram

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