2.7 GHz DDS-Based

AgileRFTM Synthesizer

AD9956

Rev. B

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FEATURES

400 MSPS internal DDS clock speed

48-bit frequency tuning word

14-bit programmable phase offset

Integrated 14-bit DAC

Excellent dynamic performance

Phase noise ≤ 135 dBc/Hz @ 1 KHz offset

−80 dB SFDR @ 160 MHz (±100 KHz offset IOUT)

25 Mb/s write-speed serial I/O control

200 MHz phase frequency detector inputs

655 MHz programmable input dividers for the phase

frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)

Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)

8 phase/frequency profiles

1.8 V supply for device operation

3.3 V supply for I/O and charge pump

Software controlled power-down

48-lead LFCSP package

Automatic linear frequency sweeping capability (in DDS)

Programmable charge pump current (up to 4 mA)

Phase modulation capability

Multichip synchronization

Dual-mode PLL lock detect

655 MHz CML-mode PECL-compliant driver

APPLICATIONS

Agile LO frequency synthesis

FM chirp source for radar and scanning systems

Automotive radars

Test and measurement equipment

Acousto-optic device drivers

FUNCTIONAL BLOCK DIAGRAM

FREQUENCY

ACCUMULATOR

PHASE

ACCUMULATOR

PHASE

OFFSET

PHASE

OFFSET

WORD

TIMING AND CONTROL LOGIC

PHASE TO

AMPLITUDE

CONVERSION

14

FTW

48

24

DAC

RF-DIVIDER

÷R

FROM PLLOSC

3

PS<2:0> RESET I/O PORT

CHARGE

PUMP

SCALER

Φ

BUFFER

BUFFER

CP_OUT

CP_RSET

PLL_LOCK/SYNC_IN

I/O_UPDATE

SYNC_OUT

REFCLK

REFCLK

CML CLOCK DRIVER

DRV DRV DRV_RSET

DAC_RSET

IOUT

IOUT

SYNC_CLK

SYSCLK

DELTA

FREQUENCY

TUNING WORD

DELTA

FREQUENCY

RAMP RATE

SYSCLK

3

LOCK

DETECT

48

19

14

DDS CORE

SYSCLK

I/O_RESET

OSCILLATOR

16

CHARGE

PUMP

PLLREF/

PLLREF

PLLOSC/

PLLOSC

÷N

÷4

÷M

Figure 1.