25AA040AX-ESLASHMS datasheet(12/28 Pages) MICROCHIP

12 / 28 page

25AA040A/25LC040A

DS21827D-page 12

2.7

Data Protection

The following protection has been implemented to

prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

•CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

2.8

Power-On State

The 25XX040A powers on in the following state:

• The device is in low-power Standby mode

(CS = 1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter active state

TABLE 2-4:

WRITE-PROTECT FUNCTIONALITY MATRIX

(pin 3)

WEL

(SR bit 1)

Protected Blocks

Unprotected Blocks

STATUS Register

(low)

Protected

(high)

Protected

(high)

Protected

Writable

= don’t care

25AA040AX-E/MS 数据表(PDF) 12 Page - Microchip Technology

25AA040AX-E/MS 数据表(HTML) 12 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载

链接网址

25AA040AX-E/MS 数据表(PDF) 12 Page - Microchip Technology

25AA040AX-E/MS 数据表(HTML) 12 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表 下载

链接网址

数据表下载