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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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LS7366R 数据表(PDF) 5 Page - LSI Computer Systems |
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LS7366R 数据表(HTML) 5 Page - LSI Computer Systems |
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5 / 13 page  DC Electrical Characteristics. (TA = -25˚C to +85°C) Parameter Symbol Min. TYP Max. Unit Remarks Supply Voltage VDD 3.0 - 5.5 V - Supply Current IDD 300 400 450 µA VDD = 3.0V IDD 700 800 950 µA VDD = 5.0V Input Voltages fCKi, Logic high VCH 2.3 - - V VDD = 3.0V VCH 3.7 - - V VDD = 5.0V fCKi, Logic Low VCL - - 0.7 V VDD = 3.0V VCL - - 1.3 V VDD = 5.0 All other inputs, Logic High VAH 2.1 - V VDD = 3.0V VAH 3.5 - V VDD = 5.0V All other inputs, Logic Low VAL - - 0.5 V VDD = 3.0V VAL - - 1.0 V VDD = 5.0V Input Currents: CNT_EN Low IIEL - 3.0 5.0 µA VAL = 0.7V, VDD = 3.0V IIEL - 10.0 15.0 µA VAL = 1.2V, VDD = 5.0V CNT_EN High IIEH - 1.0 3.0 µA VAH = 1.9V, VDD = 3.0V IIEH - 4.0 6.0 µA VAH = 3.2V, VDD = 5.0V All other inputs, High or Low - - 0 0 µA - Output Currents: LFLAG, DFLAG Sink IOFL -1.3 -2.0 - mA VOUT = 0.5V, VDD = 3.0V IOFL -3.2 -4.0 - mA VOUT = 0.5V, VDD = 5.0V LFLAG Source - 0 0 - mA Open Drain Output DFLAG Source IOFH 1.0 1.8 - mA VOUT = 2.5V, VDD = 3.0V IOFH 2.8 3.6 - mA VOUT = 4.5V, VDD = 5.0V fCKO Sink IOCL -1.3 -2.0 - mA VOUT = 0.5V, VDD = 3.0V IOCL -3.2 -4.0 - mA VOUT = 0.5V, VDD = 5.0V fCKO Source IOCH 1.3 2.0 - mA VOUT = 2.5V, VDD = 3.0V IOCH 3.2 4.0 - mA VOUT = 4.5V, VDD = 5.0V TXD/MISO: Sink IOML -1.5 -2.4 - mA VOUT = 0.5V, VDD = 3.0V IOML -3.8 -4.8 - mA VOUT = 0.5V, VDD = 5.0V Source IOMH 1.5 2.4 - mA VOUT = 2.5V, VDD = 3.0V IOMH 3.8 4.8 - mA VOUT = 4.5V, VDD = 5.0V 7366R-041906-5 Transient Characteristics. (TA = -25˚C to +85˚C, VDD = 5V ± 10%) Parameter Symbol Min. Value Max.Value Unit Remarks (See Fig. 2) SCK High Pulse Width tCH 100 - ns - SCK Low Pulse Width tCL 100 - ns - SS/ Set Up Time tCSL 100 - ns - SS/ Hold Time tCSH 100 - ns - Quadrature Mode (See Fig. 5, 7 & 8 ) fCKI High Pulse Width t1 12 - ns - fCKI Pulse Width t2 12 - ns - fCKI Frequency fFCK - 40 MHz - Effective Filter Clock fF Period t3 25 - ns t3 = t1+t2, MDR0 <7> = 0 t3 50 - ns t3 = 2(t1+t2), MDR0 <7> = 1 Effective Filter Clock fF frequency fF - 40 MHz fF = 1/ t3 Quadrature Separation t4 26 - ns t4 > t3 Quadrature Clock Pulse Width t5 52 - ns t5 ≥ 2t3 Quadrature Clock frequency fQA, fQB - 9.6 MHz fQA = fQB < 1/4t3 Quadrature Clock to Count Delay tQ1 4t3 5t3 - - x1 / x2 / x4 Count Clock Pulse Width tQ2 12 - ns tQ2 = (t3)/2 Index Input Pulse Width tid 32 - ns tid > t4 Index Set Up Time tis - 5 ns - Index Hold Time tih - 5 ns - Quadrature clock to tfl 4.5t3 5.5t3 ns - DFLAG/ or LFLAG/ delay DFLAG/ output width tfw 26 - ns tfw = t4 |
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