Data Sheet

ADAU7002

Rev. C | Page 3 of 16

SPECIFICATIONS

IOVDD = 1.8 V, TA = 25°C, BCLK = 3.072 MHz, output = 48 kHz, I2S format, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL INPUT/OUTPUT

High Level Input Voltage (VIH)

0.7 × IOVDD

V

Low Level Input Voltage (VIL)

0.3 × IOVDD

V

Input Leakage, High (IIH)

BCLK and LRCLK pins

1

µA

Input Leakage, Low (IIL)

BCLK and LRCLK pins

1

µA

Input Capacitance

5

pF

SDATA

4.5

mA

PDM_CLK

9

mA

PERFORMANCE

Dynamic Range

20 Hz to 20 kHz, −60 dB input

With A-Weighted Filter (RMS)

110

dB

Signal-to-Noise-Ratio

A-weighted, fourth-order input

110

dB

Decimation Ratio

64×

Frequency Response

DC to 0.45 output fS

−0.1

+0.01

dB

Stop Band

0.566

fS

Stop-Band Attenuation

60

dB

Group Delay

0.02 fS input signal

3.31

LRCLK cycles

Gain

PDM to PCM

0

dB

Start-Up Time

48

LRCLK cycles

Bit Width

Internal and output

20

Bits

Interchannel Phase

0

Degrees

CLOCKING

Output Sampling Rate

fS LRCLK pulse rate

4

48

96

kHz

BCLK Frequency

fBCLK

0.256

3.072

24.576

MHz

POWER SUPPLIES

Supply Voltage Range

IOVDD

1.62

3.6

V

Supply Current

IOVDD = 1.8 V

0.67

mA

IOVDD = 3.3 V

1.33

mA

IOVDD = 1.8 V, 16 kHz output

0.21

mA

IOVDD = 3.3 V, 16 kHz output

0.41

mA

Shutdown Current

IOVDDSD, no input clocks

1

µA