ADAU7002

Data Sheet

Rev. C | Page 10 of 16

Serial Port Timing

BCLK

LRCLK

SDATA

TDM MODE

SDATA

I2S JUSTIFIED

MODE

tBIH

MSB

MSB

MSB – 1

tBIL

tLIS

tLIH

tSODM

tSODM

Figure 13. Serial Port Timing Diagram

IOVDD = 1.62 V to 3.63 V, load capacitance = 25 pF, unless otherwise noted.

Table 7. I2S/TDM Timing Parameters

Parameter

Symbol

tMIN

tMAX

Unit

BCLK Pulse Width High

tBIH

10

ns

BCLK Pulse Width Low

tBIL

10

ns

LRCLK Setup Time

tLIS

10

ns

LRCLK Hold Time

tLIH

10

ns

Time from BCLK Falling

tSODM

18

ns

LRCLK

BCLK

SDATA

I2S LEFT CHANNEL

20

BCLKs

I2S RIGHT CHANNEL

TRISTATE

TRISTATE

Figure 14. I2S, CONFIG Pin Tied to IOVDD

SLOT 1

LRCLK

BCLK

SDATA

20

BCLKs

RIGHT

LEFT

SLOT 2

SLOT 3

SLOT 4

SLOT 5

SLOT 6

SLOT 7

SLOT 8

TRISTATE

TRISTATE

TRISTATE

TRISTATE

TRISTATE

TRISTATE

Figure 15. TDM8 Channel 1 and Channel 2, CONFIG Pin Tied to GND