24C02CTESLASHMS datasheet(8/24 Pages) MICROCHIP

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24C02C

DS21202G-page 8

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no ACK is returned, then the Start bit and control byte

must be re-sent. If the cycle is complete, then the

device will return the ACK and the master can then

proceed with the next Read or Write command. See

Figure 7-1 for flow diagram.

FIGURE 7-1:

ACKNOWLEDGE

POLLING FLOW

8.0

READ OPERATIONS

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

8.1

Current Address Read

The 24C02C contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous read

access was to address n, the next current address read

operation would access data from address n + 1. Upon

receipt of the slave address with the R/W bit set to one,

the 24C02C issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer, but does generate a Stop condition and the

24C02C discontinues transmission (Figure 8-1).

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24C02C as part of a write operation. After the word

address is sent, the master generates a Start condition

following the acknowledge. This terminates the write

operation, but not before the internal Address Pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24C02C will then

issue an acknowledge and transmits the eight bit data

word. The master will not acknowledge the transfer but

does generate a Stop condition and the 24C02C

discontinues transmission (Figure 8-2). After this

command, the internal address counter will point to the

address location following the one that was just read.

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24C02C transmits

the first data byte, the master issues an acknowledge

as opposed to a Stop condition in a random read. This

directs the 24C02C to transmit the next sequentially

addressed 8-bit word (Figure 8-3).

To provide sequential reads, the 24C02C contains an

internal Address Pointer which is incremented by one

at the completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operation. The internal Address

Pointer will automatically roll over from address FF to

address 00.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

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