AM29243EH datasheet(14/36 Pages) AMD

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P R E L I M I N A R Y

Am29240 EH Microcontroller Series

™

TRIST

Three-State Control

(input, asynchronous, pull-up resistor)

This input is asserted to force all processor outputs into

the high-impedance state. This signal is tied High

through an internal pull-up resistor.

TRST

Test Reset Input

(input, asynchronous, pull-up resistor)

This input asynchronously resets the Test Access Port.

If TRST is not driven, it appears High internally. TRST

must be tied to RESET, even if the Test Access Port is

not being used.

TXDA

Transmit Data, Port A (output, asynchronous)

This output is used to transmit serial data from Serial

Port A.

TXDB

Transmit Data, Port B (output, asynchronous)

This output is used to transmit data from Serial Port B.

This signal is supported on the Am29240EH and

Am29243EH microcontrollers only.

UCLK

UART Clock (input)

This is an oscillator input for generating the UART (Seri-

al Port) clock. To generate the UART clock, the oscillator

frequency may be divided by any amount up to 65,536.

The UART clock operates at 16 times the Serial Port’s

baud rate. As an option, UCLK may be driven with

MEMCLK or INCLK. It can be driven with TTL levels.

VCLK

Video Clock (input, asynchronous)

This clock is used to synchronize the transfer of video

data. As an option, VCLK may be driven with MEMCLK

or INCLK. It can be driven with TTL levels. This signal is

supported on the Am29240EH and Am29245EH mi-

crocontrollers only.

VDAT

Video Data (input/output, synchronous to VCLK)

This is serial data to or from the video device. This signal

is supported on the Am29240EH and Am29245EH mi-

crocontrollers only.

WAIT

Add Wait States

(input, synchronous, internal pull-up)

External accesses are normally timed by the processor.

However, the WAIT signal may be asserted during a PIA,

ROM, or DMA access to extend the access indefinitely.

For external DMA accesses, the number of wait states

taken by the DRAM controller (this includes peripheral

read and write wait states during DMA transfers) is deter-

mined by the actual value in the DMAWAIT field of the

DMA Control Register or the number of wait states speci-

fied by the IOWAIT field in the PIA Control Register,

whichever is greater.

WARN

Warn (input, asynchronous, edge-sensitive,

internal pull-up)

A High-to-Low transition on this input causes a non-

maskable WARN trap to occur. This trap bypasses the

normal trap vector fetch sequence, and is useful in situa-

tions where the vector fetch may not work (e.g., when

data memory is faulty). This signal has special harden-

ing against metastable states, allowing it to be driven

with a slow-transition-time signal. WARN must be held

active for at least four system clocks for the processor to

recognize it.

Write Enable (output, synchronous)

This signal is used to write the selected DRAM bank.

“Early write” cycles are used so the DRAM data inputs

and outputs can be tied to the common ID Bus.

PRODUCT ENHANCEMENTS

Programmable DRAM Timing

Through Bit 24 in the DRAM Control Register, the DRAM

controller now supports programmable DRAM timing,

for either two- or three-cycle simple accesses, with

single-cycle page-mode accesses. The new bit defined

below.

Bit 24: Programmable DRAM Timing (PDT)—A 1 in

this bit sets the DRAM timing to 2/1, for two-cycle simple

accesses and single-cycle page-mode accesses. A 0 in

this bit sets the DRAM timing to 3/1, for three-cycle sim-

ple accesses and single-cycle page-mode accesses.

FEATURES NO LONGER SUPPORTED

The following features are no longer supported on the

Am29240EH, Am29245EH, and Am29243EH micro-

controllers:

33 MHz operating frequency

Scalable Clocking

™ technology (also known as

turbo mode or clock doubling)

16-bit DRAM memory

MEMDRV signal

MEMCLK as an input

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