ADA4961

Data Sheet

Rev. C | Page 18 of 24

Pin No.

Mnemonic

Description

Basic Connection

SPI/Parallel

Control

6

MODE

Parallel, serial mode

control

Connect this pin to a 3.3 V compliant logic control. Logic 0 asserts serial control,

and Logic 1 asserts parallel control.

7

SDIO

SPI data IO

Connect this pin to a 3.3 V compliant logic control.

8

A4/SCLK

SPI clock, parallel mode

gain control, Bit 4

Connect this pin to a 3.3 V compliant logic control.

9

A3/CS

SPI chip select, parallel

mode gain control, Bit 3

Connect this pin to a 3.3 V compliant logic control.

10

A2/FA

Fast attack enable,

parallel mode gain

control, Bit 2

Connect this pin to a 3.3 V compliant logic control. Logic 1 asserts FA enabled,

and Logic 0 asserts FA disabled.

11

A1

Parallel mode gain

control, Bit 1

Connect this pin to a 3.3 V compliant logic control.

12

A0

Parallel mode gain

control, Bit 0

Connect this pin to a 3.3 V compliant logic control.

13

LATCH

Parallel mode latch

control

Connect this pin to a 3.3 V compliant logic control. Logic 0 asserts transparent

mode, and Logic 1 asserts latched mode.

19

PWUP

Power up

Connect this pin to a 3.3 V compliant logic control. Logic 1 asserts power-up, and

Logic 0 asserts power-down.

20

PM

Performance mode

Connect this pin to a 3.3 V compliant logic control. Logic 1 asserts low

performance mode, and Logic 0 asserts high performance mode.

2nH

0.5µF

0.5µF

+5.0V

+5.0V

AD9625

AC

1:2

DIGITAL

INTERFACE

ADA4961

2nH

VIN+

VIN–

MARKI

BAL-0006GSMG

BAND-PASS

FILTER

50Ω

0.1µF

0.1µF

0.1µF

0.1µF

10Ω

10Ω

50Ω

50Ω

1.5pF

100Ω

VCOM

+5.0V

Figure 41. Wideband ADC Interfacing Example Featuring the ADA4961 and the AD9625

ADC DRIVING

The ADA4961 is a high output linearity variable gain amplifier

optimized for ADC interfacing. The output IMDs and noise

floor remain constant throughout the 22 dB gain range. This is a

valuable feature in a variable gain receiver, where it is desirable to

maintain a constant, instantaneous dynamic range as the receiver

range is modified. The output noise is 6.9 nV/√Hz, which is

compatible with 14-bit or 16-bit ADCs. The two-tone IMDs are

typically greater than −75 dBc for a 5.5 dBm composite signal into

50 Ω or a 1.2 V p-p composite output. The 50 Ω output

impedance makes the task of designing a filter for the high

input impedance ADCs more straightforward.

Figure 41 shows the ADA4961 driving a two-pole, 1 GHz, low-

pass filter into the AD9625. The AD9625 is a 12-bit, 2.5 GSPS

ADC with a buffered wideband input that presents a 100 Ω

differential input impedance and requires a 1.2 V input swing to

reach full scale. For optimum performance, drive the ADA4961

differentially, using a high performance 1:2 matching balun.