AD8038/AD8039

Rev. G | Page 13 of 16

LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS

DISABLE

The AD8038 in the 8-lead SOIC package provides a disable

feature. This feature disables the input from the output (see

Figure 42 for input-output isolation) and reduces the quiescent

current from typically 1 mA to 0.2 mA. When the DISABLE

node is pulled below 4.5 V from the positive supply rail, the part

becomes disabled. To enable the part, the DISABLE node needs

to be pulled to greater than (VS – 2.5).

POWER SUPPLY BYPASSING

Power supply pins are actually inputs, and care must be taken

so that a noise-free stable dc voltage is applied. The purpose of

bypass capacitors is to create low impedances from the supply

to ground at all frequencies, thereby shunting or filtering a

majority of the noise.

Decoupling schemes are designed to minimize the bypassing

impedance at all frequencies with a parallel combination of

capacitors. The 0.01 μF or 0.001 μF (X7R or NPO) chip capacitors

are critical and should be placed as close as possible to the

amplifier package. Larger chip capacitors, such as 0.1 μF

capacitors, can be shared among a few closely spaced active

components in the same signal path. A 10 μF tantalum capacitor

is less critical for high frequency bypassing and, in most cases,

only one per board is needed at the supply inputs.

GROUNDING

A ground plane layer is important in densely packed PC boards

to spread the current minimizing parasitic inductances. However,

an understanding of where the current flows in a circuit is critical

to implementing effective high speed circuit design. The length

of the current path is directly proportional to the magnitude of

parasitic inductances and, therefore, the high frequency impedance

of the path. High speed currents in an inductive ground return

create an unwanted voltage noise.

The length of the high frequency bypass capacitor leads is most

critical. A parasitic inductance in the bypass grounding works

against the low impedance created by the bypass capacitor. Because

load currents flow from the supplies as well, the ground for the

load impedance should be at the same physical location as the

bypass capacitor grounds. For the larger value capacitors, which

are intended to be effective at lower frequencies, the current

return path distance is less critical.

INPUT CAPACITANCE

Along with bypassing and ground, high speed amplifiers can be

sensitive to parasitic capacitance between the inputs and ground. A

few picofarads of capacitance reduces the input impedance at

high frequencies, in turn increasing the gain of the amplifiers,

causing peaking of the frequency response, or even oscillations

if severe enough. It is recommended that the external passive

components that are connected to the input pins be placed as

close as possible to the inputs to avoid parasitic capacitance.

The ground and power planes must be kept at a distance of at

least 0.05 mm from the input pins on all layers of the board.

OUTPUT CAPACITANCE

To a lesser extent, parasitic capacitances on the output can cause

peaking of the frequency response. Two methods to minimize

this effect include the following:

•

Put a small value resistor in series with the output to isolate

the load capacitor from the output stage of the amplifier, see

Figure 12, Figure 13, Figure 27, and Figure 28.

•

Increase the phase margin with higher noise gains or add

a pole with a parallel resistor and capacitor from −IN to

the output.

INPUT-TO-OUTPUT COUPLING

The input and output signal traces should not be parallel to

minimize capacitive coupling between the inputs and outputs,

avoiding any positive feedback.