M41ST85W datasheet(12/34 Pages) STMICROELECTRONICS

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M41ST85W

12/34

WRITE Mode

In this mode the master transmitter transmits to

the M41ST85W slave receiver. Bus protocol is

shown in Figure 14.. Following the START condi-

tion and slave address, a logic '0' (R/W=0) is

placed on the bus and indicates to the addressed

device that word address An will follow and is to be

written to the on-chip address pointer. The data

word to be written to the memory is strobed in next

and the internal address pointer is incremented to

the next memory location within the RAM on the

reception

acknowledge

clock.

The

M41ST85W slave receiver will send an acknowl-

edge clock to the master transmitter after it has re-

ceived

the

slave

address

(see

Figure

11., page 10) and again after it has received the

word address and each data byte.

Figure 14. WRITE Mode Sequence

Data Retention Mode

With valid VCC applied, the M41ST85W can be ac-

cessed as described above with READ or WRITE

Cycles. Should the supply voltage decay, the

M41ST85W will automatically deselect, write pro-

tecting itself (and any external SRAM) when VCC

falls between VPFD(max) and VPFD(min). This is

accomplished by internally inhibiting access to the

clock registers. At this time, the Reset pin (RST) is

driven active and will remain active until VCC re-

turns to nominal levels. External RAM access is in-

hibited in a similar manner by forcing ECON to a

high level. This level is within 0.2 volts of the VBAT.

ECON will remain at this level as long as VCC re-

mains at an out-of-tolerance condition. When VCC

falls below the Battery Back-up Switchover Volt-

age (VSO), power input is switched from the VCC

pin to the SNAPHAT® battery, and the clock regis-

ters and external SRAM are maintained from the

attached battery supply.

All outputs become high impedance. The VOUT pin

is capable of supplying 100 µA of current to the at-

tached memory with less than 0.3 volts drop under

this condition. On power up, when VCC returns to

a nominal value, write protection continues for trec

by inhibiting ECON. The RST signal also remains

active during this time (see Figure 22., page 27).

Note: Most low power SRAMs on the market to-

day can be used with the M41ST85W RTC SU-

PERVISOR. There are, however some criteria

which should be used in making the final choice of

an SRAM to use. The SRAM must be designed in

a way where the chip enable input disables all oth-

er inputs to the SRAM. This allows inputs to the

M41ST85W and SRAMs to be “Don’t Care” once

VCC falls below VPFD(min). The SRAM should also

guarantee data retention down to VCC=2.0 volts.

The chip enable access time must be sufficient to

meet the system needs with the chip enable output

propagation delays included. If the SRAM includes

a second chip enable pin (E2), this pin should be

tied to VOUT.

If data retention lifetime is a critical parameter for

the system, it is important to review the data reten-

tion

current

specifications

for

the

particular

SRAMs being evaluated. Most SRAMs specify a

data retention current at 3.0 volts. Manufacturers

generally specify a typical condition for room tem-

perature along with a worst case condition (gener-

ally at elevated temperatures). The system level

requirements will determine the choice of which

value to use. The data retention current value of

the SRAMs can then be added to the IBAT value of

the M41ST85W to determine the total current re-

quirements for data retention. The available bat-

tery capacity for the SNAPHAT® top of your choice

can then be divided by this current to determine

the amount of data retention available (see Table

19., page 32).

For a further more detailed review of lifetime calcu-

lations, please see Application Note AN1012.

AI00591

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

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