ADA4817-1ACPZ-R7 datasheet(19/29 Pages) AD

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Data Sheet

ADA4817-1/ADA4817-2

THEORY OF OPERATION

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Rev. H | 19 of 29

Figure 55. DC Errors of the Voltage Feedback Amplifier

The voltage error due to Ib+ and Ib− is minimized if RS = RF ||

RG (though with the ADA4817-1/ADA4817-2 input currents in the

picoamp range, this is likely not a concern). To include common-

mode effects and power supply rejection effects, total VOS can be

modeled by

VOS=VOSnom+ ΔVSPSRR+ΔVCMCMRR

(10)

where:

VOS is the offset voltage.

VOSnom is the offset voltage specified at nominal conditions.

ΔVS is the change in power supply from nominal conditions.

PSRR is the power supply rejection ratio in V/V.

ΔVCM is the change in common-mode voltage from nominal condi-

tions.

CMRR is the common-mode rejection ratio in V/V.

WIDEBAND OPERATION

The ADA4817-1/ADA4817-2 provides excellent performance as a

high speed buffer. Figure 52 shows the circuit used for wideband

characterization for high gains. The impedance at the summing

junction (RF || RG) forms a pole in the loop response of the amplifier

with the input capacitance of the amplifier of 1.3 pF. This pole can

cause peaking and ringing if its frequency is too low. Feedback

resistances of 100 Ω to 400 Ω are recommended because they

minimize the peaking and they do not degrade the performance of

the output stage. Peaking in the frequency response can also be

compensated for with a small feedback capacitor (CF) in parallel

with the feedback resistor, or a series resistor in the noninverting

input, as shown in Figure 56.

The distortion performance depends on the following variables:

►

The closed-loop gain of the application

►

Whether it is inverting or noninverting

►

Amplifier loading

►

Signal frequency and amplitude

►

Board layout

The best performance is usually obtained in the G + 1 configuration

with no feedback resistance, big output load resistors, and small

board parasitic capacitances.

DRIVING CAPACITIVE LOADS

In general, high speed amplifiers have a difficult time driving capaci-

tive loads. This is particularly true in low closed-loop gains, where

the phase margin is the lowest.

The difficulty arises because the load capacitance, CL, forms a pole

with the output resistance, RO, of the amplifier. The pole can be

described by the following equation:

fP= 12πROCL

(11)

If this pole occurs too close to the unity-gain crossover point, the

phase margin degrades. Degradation is due to the additional phase

loss associated with the pole.

Note that such capacitance introduces significant peaking in the

frequency response. Larger capacitance values can be driven but

must use a small series resistor, RSNUB, at the output of the

amplifier, as shown in Figure 56. Adding RSNUB creates a zero that

cancels the pole introduced by the load capacitance. Typical values

for RSNUB can range from 10 Ω to 50 Ω. The value is typically

based on the circuit requirements. Figure 56 also shows another

way to reduce the effect of the pole created by the capacitive load

(CL) by placing a capacitor (CF) in the feedback loop parallel to the

feedback resistor Typical capacitor values can range from 0.5 pF to

2 pF. Figure 59 shows the effect of adding a feedback capacitor to

the frequency response.

Figure 56. RSNUB or CF Used to Reduce Peaking

THERMAL CONSIDERATIONS

With 10 V power supplies and 19 mA quiescent current, the

ADA4817-1/ADA4817-2 dissipate 190 mW with no load. This im-

plies that with the thermal resistances listed in Table 4, the junc-

tion temperature is typically almost 25°C higher than the ambient

temperature. The ADA4817-1/ADA4817-2 can maintain a constant

bandwidth over temperature; therefore, an initial ramp up of the

current consumption during warm-up is expected. VOS can change

up to 0.3 mV due to warm-up effects for an ADA4817-1/ADA4817-2

on ± 5 V. The input bias current typically increases by a factor of 1.7

for every 10°C rise in temperature.

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