ADA4817-1ACPZ-R7 datasheet(21/29 Pages) AD

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Data Sheet

ADA4817-1/ADA4817-2

THEORY OF OPERATION

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Rev. H | 21 of 29

HIGHER FREQUENCY ATTENUATION

There is another package variation problem between the SOIC and

the LFCSP package. The SOIC package shows approximately 1 dB

to 1.5 dB of additional peaking at a gain of 1, due to the parasitic

capacitances in the SOIC package, which is not recommended for

very high frequency parts that exceed 1 GHz. A good approach

to reduce the peaking is to place a resistor, RS, in series with the

noninverting input, which creates a first-order pole formed by RS

and CIN, the common-mode input capacitance.

Figure 60 shows the higher frequency attenuation, which reduces

the peaking but also reduces the −3 dB bandwidth.

Figure 60. Small Signal Frequency Response for Various RS (SOIC)

As shown in Figure 60, the peaking dropped by almost 2 dB when

RS = 0 Ω to RS = 100 Ω, and in return, the −3 dB bandwidth

dropped from 1 GHz to 700 MHz. To maintain the −3 dB bandwidth

and to reduce peaking, an RLC circuit is recommended instead of

RS, as shown in Figure 61.

Figure 61. RLC Circuit

The R in parallel to the series LC forms a notch that can be shaped

to compensate for the peaking produced by the amplifier. The result

is a smooth 1 GHz −3 dB bandwidth, 250 MHz 0.1 dB flatness,

and less than 1 dB of peaking. Place this circuit in the path of the

noninverting input when the ADA4817-1/ADA4817-2 are used at a

gain of 1. The RLC values may need adjustment depending on the

source impedance and the flatness and bandwidth required. Figure

62 shows the frequency response after the RLC circuit is in place.

Figure 62. Frequency Response with RLC Circuit

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