ADA4851-1/ADA4851-2/ADA4851-4

Rev. J | Page 18 of 24

Figure 42 illustrates how the rising edge settling time for the

amplifier is configured as a unity-gain follower, stretching out

as the top of a 1 V step input that approaches and exceeds the

specified input common-mode voltage limit.

For signals approaching the negative supply and inverting gain

and high positive gain configurations, the headroom limit is the

output stage. The ADA4851-1/ADA4851-2/ADA4851-4 amplifiers

use a common emitter output stage. This output stage maximizes

the available output range, limited by the saturation voltage of

the output transistors. The saturation voltage increases with the

drive current that the output transistor is required to supply due

to the collector resistance of the output transistor.

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

0

1020

3040

50

6070

8090

100

TIME (ns)

3.6

VSTEP = 2V TO 3V

VSTEP = 2.1V TO 3.1V

VSTEP = 2.2V TO 3.2V

VSTEP = 2.3V TO 3.3V

VSTEP = 2.4V TO 3.4V

G = +1

RL = 1kΩ

VS = 5V

Figure 42. Output Rising Edge for 1 V Step at Input Headroom Limits

As the saturation point of the output stage is approached, the

output signal shows increasing amounts of compression and

clipping. As in the input headroom case, higher frequency

signals require slightly more headroom than the lower fre-

quency signals. Figure 16 illustrates this point by plotting the

typical harmonic distortion vs. the output amplitude.

OVERLOAD BEHAVIOR AND RECOVERY

Input

The specified input common-mode voltage of the ADA4851-1/

ADA4851-2/ADA4851-4 is 200 mV below the negative supply

to within 2.2 V of the positive supply. Exceeding the top limit

results in lower bandwidth and increased rise time, as shown in

Figure 41 and Figure 42. Pushing the input voltage of a unity-

gain follower to less than 2 V from the positive supply leads to

the behavior shown in Figure 43—an increasing amount of output

error as well as a much increased settling time. The recovery time

from input voltages of 2.2 V or closer to the positive supply is

approximately 55 ns, which is limited by the settling artifacts

caused by transistors in the input stage coming out of saturation.

The amplifiers do not exhibit phase reversal, even for input

voltages beyond the voltage supply rails. Going more than 0.6 V

beyond the power supplies turns on protection diodes at the input

stage, which greatly increases the current draw of the devices.

TIME (ns)

2.00

2.25

2.50

3.00

3.25

3.50

2.75

0

100

200

300

400

500

600

700

800

900

1k

G = +1

RL = 1kΩ

VS = 5V

VSTEP = 2.25V TO 3.25V

VSTEP = 2.25V TO

3.5V, 4V, AND 5V

Figure 43. Pulse Response of G = +1 Follower, Input Step Overloading

the Input Stage

Output

Output overload recovery is typically within 35 ns after the

input of the amplifier is brought to a nonoverloading value.

Figure 44 shows output recovery transients for the amplifier

configured in an inverting gain of 1 recovering from a saturated

output from the top and bottom supplies to a point at midsupply.

–2

–1

0

1

2

3

4

5

6

0

1020

3040

50

6070

8090

100

TIME (ns)

7

G = –1

RL = 1kΩ

VS = 5V

INPUT

VOLTAGE

EDGES

VOUT = 5V TO 2.5V

VOUT = 0V TO 2.5V

Figure 44. Overload Recovery