TUSB4041IPAPRG4 datasheet(15/48 Pages) TI

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TUSB4041I

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SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017

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8.4 Device Functional Modes

8.4.1 External Configuration Interface

The TUSB4041I device supports a serial interface for configuration register access. The device can be

configured by an attached I2C EEPROM or accessed as a slave by an SMBus-capable host controller. The

external interface is enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the

deassertion of reset. The mode, I2C master or SMBus slave, is determined by the state of SMBUSz pin at reset.

8.4.2 I2C EEPROM Operation

The TUSB4041I device supports a single-master, standard mode (100 kb/s) connection to a dedicated I2C

EEPROM when the I2C interface mode is enabled. In I2C mode, the TUSB4041I device reads the contents of the

EEPROM at bus address 1010000b using 7-bit addressing starting at address 0.

If the value of the EEPROM contents at byte 00h equals 55h, the TUSB4041I device loads the configuration

registers according to the EEPROM map. If the first byte is not 55h, the TUSB4041I device exits the I2C mode

and continues execution with the default values in the configuration registers. The hub does not connect on the

upstream port until the configuration is completed. If the hub detected an unprogrammed EEPROM (value other

than 55h), the hub enters programming mode and a programming endpoint within the hub is enabled.

NOTE

The bytes located above offset Ah are optional. The requirement for data in those

addresses is dependent on the options configured in the Device Configuration Register

and Device Configuration Register 2.

For details on I2C operation, refer to the UM10204 I2C-bus Specification and User Manual.

8.4.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB4041I device supports read block and write block

protocols as a slave-only SMBus device.

The TUSB4041I device slave address is 1000 1xyz, where:

•

x is the state of GANGED/SMBA2/HS_UP pin at reset

•

y is the state of FULLPWRMGMTz/SMBA1 pin at reset

•

z is the read-write (R/W) bit; 1 = read access, 0 = write access

If the TUSB4041I device is addressed by a host using an unsupported protocol, the device does not respond.

The TUSB4041I device waits indefinitely for configuration by the SMBus host and does not connect on the

upstream port until the SMBus host indicates configuration is complete by clearing the CFG_ACTIVE bit.

For details on SMBus requirements, refer to the System Management Bus (SMBus) Specification.

NOTE

During the SMBUS configuration the hub may draw an extra current, this extra current

consumption will end as soon as the CFG_ACTIVE bit is cleared. For more information

refer to Hub Input Supply Current section in this datasheet.

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