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TUSB4041I

SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017

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Copyright © 2015–2017, Texas Instruments Incorporated

Table of Contents

1

Features .................................................................. 1

2

Applications ........................................................... 1

3

Description ............................................................. 1

4

Revision History..................................................... 2

5

Description (continued)......................................... 3

6

Pin Configuration and Functions ......................... 4

7

Specifications......................................................... 8

7.1

Absolute Maximum Ratings ...................................... 8

7.2

ESD Ratings ............................................................ 8

7.3

Recommended Operating Conditions ....................... 9

7.4

Thermal Information .................................................. 9

7.5

3.3-V I/O Electrical Characteristics ........................... 9

7.6

Power-Up Timing Requirements ............................. 10

7.7

Hub Input Supply Current ....................................... 10

8

Detailed Description ............................................ 11

8.1

Overview ................................................................. 11

8.2

Functional Block Diagram ....................................... 11

8.3

Feature Description................................................. 12

8.4

Device Functional Modes........................................ 15

8.5

Register Maps ......................................................... 16

9

Application and Implementation ........................ 29

9.1

Application Information............................................ 29

9.2

Typical Application .................................................. 29

10

Power Supply Recommendations ..................... 36

10.1

TUSB4041I Power Supply .................................... 36

10.2

Downstream Port Power ....................................... 36

10.3

Ground .................................................................. 36

11

Layout................................................................... 37

11.1

Layout Guidelines ................................................. 37

11.2

Layout Example .................................................... 38

12

Device and Documentation Support ................. 39

12.1

Documentation Support ........................................ 39

12.2

Receiving Notification of Documentation Updates 39

12.3

Community Resource............................................ 39

12.4

Trademarks ........................................................... 39

12.5

Electrostatic Discharge Caution ............................ 39

12.6

Glossary ................................................................ 39

13

Mechanical, Packaging, and Orderable

Information ........................................................... 39

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (July 2017) to Revision E

Page

•

Changed smbusRst From: Bit 6 To: Bit 1, and cfgActive1 From: Bit 5 To: Bit 0 Table 25 ................................................. 28

Changes from Revision C (September 2016) to Revision D

Page

•

Deleted paragraph: "Each bit corresponds directly to a downstream port. For example: used0 corresponds to

downstream port 1, used1 corresponds to downstream port 2, and so on. All combinations are supported with the

exception of both ports 1 and 3 marked as disabled." from Table 12 .................................................................................. 21

Changes from Revision B (December 2015) to Revision C

Page

•

Added SMBUS Programming current to Hub Input Supply Current .................................................................................... 10

•

Added NOTE to the SMBus Slave Operation section ......................................................................................................... 15

•

Added text "This device will always report the XORed PID LSB value of 0x42" to the Description of Table 7 .................. 18

Changes from Revision A (September 2015) to Revision B

Page

•

Changed the configuration of the PWRCTL_POL pin (R17) in the Clock, Reset, and Miscellaneous section .................... 34

Changes from Original (July 2015) to Revision A

Page

•

Changed pin number for USB_DP_DN1 and USB_DP_DN2 in the Pin Functions table ...................................................... 6