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PI3VDP411LS 数据表(PDF) 5 Page - Pericom Semiconductor Corporation |
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PI3VDP411LS 数据表(HTML) 5 Page - Pericom Semiconductor Corporation |
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5 / 11 page ![]() 5 PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter Pin Name Type Description OUT_D2+ TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal with OUT_D2–. OUT_D2– TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D2– makes a differential output signal with OUT_D2+. OUT_D1+ TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal with OUT_D1–. OUT_D1– TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D1– makes a differential output signal with OUT_D1+. HPD_SINK 5V tolerance single-ended input Low Frequency, 0V to 5V (nominal) input signal. This signal comes from the HDMI connector. Voltage High indicates "plugged" state; voltage low indicated "unplugged". HPD_SINK is pulled down by an integrated 100K ohm pulldown resistor. HPD_SOURCE 3.3V single-ended output HPD_SOURCE: 0V to 3.3V (nominal) output signal. This is level-shiftedversion of the HPD_SINK signal. SCL_SOURCE Single-ended 3.3V open-drain DDC I/O 3.3V DDC Data I/O. Pulled up by external termina- tion to 3.3V. Connected to SCL_SINK through volt- age-limiting intergrated NMOS passgate. SDA_SOURCE Single-ended 3.3V open-drain DDC I/O 3.3V DDC Data I/O. Pulled up by external termination to 3.3V. Connected to SDA_SINK through voltage- limiting intergrated NMOS passgate. SCL_SINK Single-ended 5V open-drain DDC I/O 5V DDC Clock I/O. Pulled up by external termination to 5V. Connected to SCL_SOURCE through voltage- limiting integrated NMOS passgate. SDA_SINK Single-ended 5V open-drain DDC I/O 5V DDC Data I/O. Pulled up by external termination to 5V. Connected to SDA_SOURCE through voltage- limiting integrated NMOS passgate. DDC_EN 5.0V tolerant Single-ended input Enables bias voltage to the DDC passgate level shifter gates. (May be implemented as a bias voltage connec- tion to the DDC pass gates themselves.) DDC_EN Passgate 0V Disabled 3.3V Enabled VCC3V 3.3V DC Supply 3.3V ± 10% OC_2 (1) (REXT) 3.3V single-ended control input Acceptable connections to OC_1 (REXT) pin are: Re- sistor to GND; Resistor to 3.3V; NC. (Resistor should be 0-ohm). Note: 1) internal 100Kohm pull-up 07-0198 |
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