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PACE1757ME 数据表(PDF) 9 Page - Pyramid Semiconductor Corporation

部件名 PACE1757ME
功能描述  COMPLETE EMBEDDED CPU SUBSYSTEM
PDF  34 Pages
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制造商  PYRAMID [Pyramid Semiconductor Corporation]
网页  http://www.pyramidsemiconductor.com
标志 PYRAMID - Pyramid Semiconductor Corporation

PACE1757ME 数据表(HTML) 9 Page - Pyramid Semiconductor Corporation

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PACE 1757 M/ME
Page 9 of 34
Document # MICRO-10 REV B
SIGNAL PROPAGATION DELAYS (cont'd)
Symbol
Description
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
TD/I(EXT ADR)
V
MMU Cache Hit
25
23
23
23
TSTRBD(EXT ADR ER) External Address Error
25
20
18
16
TIBD
V(EDC GEN)V
Error Correction Write Cycle
30
25
24
23
TC(GNT)
Arbiter Priority Transition
35
25
22
18
TC(RDYA)
Address Ready
30
25
21
17
TIBDIN(MEM PAR ER)
Parity Mode
34
30
28
25
TC(MEM PRT ER)
Memory Protect Error
50
45
43
40
T
STRBD (WR PROT) Write Protect Cache Hit
25
20
18
16
TC(WR PROT)I
Write Protect Cache Miss
25
22
20
18
TD/I(PROT FLAG)
Cache Hit (BPU Protection Error)
40
45
42
40
TD/I(PROT FLAG)
Cache Hit (MMU Key-Lock Error)
40
35
33
30
TC(PROT FLAG)
Cache Hit (BPU Protection Error)
25
35
33
30
TC(PROT FLAG)
Cache Hit (MMU Key-Lock Error)
25
20
20
20
TC(EXT ADR)
V
Clock to EXT Address Valid (Miss)
32
30
27
23
TFC(IB OUT)
V
Clock to EXT Address Valid (Miss)
30
25
25
25
T
EX RDY1(RDYD)
Ready Data
28
24
23
21
T
EX RDY(RDYD)
Ready Data
16
13
12.5
11.5
TC (RDYD)
V
Ready Data
28
22
19
16
TSTRBAh(A)
V
Address Valid
29
21
20
19
TIBA
V(A )V
Address Valid
31
22
21
20
TFC (R)
L
Read Strobes
24
18
15
12
TSTRBD
H(R)H
Read Strobes
24
18
15
12
TSTRBD
H(W)L
Write Strobes
262018
15
TSTRBD
L(W)H
Write Strobes
262018
15
TSTRBD(STRTROM)
Start-Up ROM
26
20
18
15
TC(TIM CLK)
Timer Clock
30
25
23
20
TEXT AD(FC B3)
Extended Address Set-Up
10
10
10
10
TF(F), TI(I)
Edge Sensitive Pulse Width
5555
tr, tf
Clock Rise and Fall Time
5
5
5
5
20 MHz
30 MHz
35 MHz
40 MHz
Note
All timing parameters are composed of Three elements. The first "T" stands for timing. The second represents the "from" signal. The third in
parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "E" or the falling edge "FC" is referenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
Units = ns



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