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PACE1753 数据表(PDF) 4 Page - Pyramid Semiconductor Corporation

部件名 PACE1753
功能描述  SINGLE CHIP, 40MHz CMOS MMU/COMBO
PDF  21 Pages
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制造商  PYRAMID [Pyramid Semiconductor Corporation]
网页  http://www.pyramidsemiconductor.com
标志 PYRAMID - Pyramid Semiconductor Corporation

PACE1753 数据表(HTML) 4 Page - Pyramid Semiconductor Corporation

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PACE1753
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Document # MICRO-4 REV D
AC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V)
20 MHz
30MHz
40 MHz
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Unit
TD/
I (EXT ADR)V
MMU Cache Hit
25
23
23
ns
T
STRBD (EXT ADR ERR)L External Address Error
25
20
16
ns
TC (IBD CORR)
Error Correction Read Cycle
25
20
19
ns
IBDV (SING ERR)H
Error Correction Read Cycle
35
30
25
ns
TC (SING ERR)L
Error Correction Read Cycle
25
20
12
ns
TIBDV (EDC GEN)V
EDAC or Parity Write Cycle
30
25
23
ns
TSTRBD (EX RDY)L
MMU Cache Miss
25
20
12
ns
TC (EX RDY)H
MMU Cache Miss
25
20
12
ns
TC (
WR PROT)L
MMU Cache Miss
25
22
18
ns
T
STRBDH (WR PROT)H
MMU Cache Miss
25
20
16
ns
TC (
GNT1)H
Arbiter LOW to HIGH Priority
35
25
18
ns
TC (
GNT0)L
Arbiter LOW to HIGH Priority
35
25
18
ns
TC (
GNT0)H
Arbiter HIGH to LOW Priority
35
25
18
ns
TC (
GNT1)L
Arbiter HIGH to LOW Priority
35
25
18
ns
TC (RDYA)
Address Ready
30
25
17
ns
TFC (IB OUT)V
Clock to IB Out Valid (I/O Read)
30
28
25
ns
TIBDIN (MEM PAR ERR)
Parity Mode
34
30
25
ns
TC (
MEM PRT ERR)
Memory Protect Error
50
45
40
ns
T
STRBD (WR PROT)
Write Protect Cache Hit
25
20
16
ns
TC (
WR PROT)L
Write Protect Cache Miss
25
22
18
ns
T
STRBDH (WR PROT)H
Write Protect Cache Miss
25
22
18
ns
TD/
I (PROT FLAG)
Cache Hit (BPU Protection Error)
50
45
40
ns
TD/
I (PROT FLAG)
Cache Hit (MMU Key-Lock Error)
40
35
30
ns
TC (PROT FLAG)
Cache Miss (BPU Protection Error)
45
35
30
ns
TC (PROT FLAG)
Cache Hit (MMU Key-Lock Error)
25
20
20
ns
TC (EXT ADR)
Clock to EXT ADR Valid (Miss)
32
30
23
ns
Notes:
1. 4.5V
≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. VIL = –3.0V for pulse widths less than or equal to 20ns.
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
4. Pulse width of
WR PROT/PROT FLAG shall be
≥ 80% of STRBD pulse width.



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