PACE1753

Page 13 of 21

Document # MICRO-4 REV D

PIN FUNCTIONS

Symbol

Name

Description

Active LOW inputs that indicate a requirement for the bus from 4

masters on the bus. The master assigned to pin

highest priority; the master assigned to pin

priority.

BUS LOCK

An active LOW input that indicates that the one master assigned

the bus is using the bus. A new master will receive a bus grant only

after this signal becomes inactive.

Active LOW outputs indicating which master was granted the

bus. It remains active during

BUS LOCK unless a higher master

request occurs, which resets it. However, the higher master will be

granted the bus only after the present master’s

BUS LOCK releases

the bus.

M/

IO

Memory or I/O

An input signal that indicates whether the current bus cycle is a

memory (HIGH) or l/O (LOW) cycle.

D/

I

Data or Instruction

An input signal that indicates whether the current bus cycle access

is for data (HIGH) or instruction (LOW).

R/

W

Read or Write

An input signal that indicates the direction of data flow on the bus.

A HIGH indicates a memory read or input operation into the master

and a LOW indicates a memory write or output operation from the

master.

STRBA

Address Strobe

An active HIGH input used to latch the address at the HIGH-to-

LOW transition of the strobe.

STRBD

Data Strobe

An active LOW input used to strobe data in memory and I/O cycles.

CPU-CLK

CPU Clock

A single-phase input clock signal (0-40MHz, 40% to 60% duty

cycle.)

RESET

Reset

An active LOW input that initializes the device.

Access Key

Active HIGH inputs used to match the access lock in the MMU page

for memory accesses. A mismatch will cause the

MEM PRT ERR

signal to become active.

Address State

Active HIGH inputs that select the page register group in the MMU.

In the DMA physical demultiplexed mode, AS(0:1) will receive the

9th and 10th most significant bits of the physical address for use in

the BPU function.

Extended Addresses Bus A bi-directional active HIGH bus. In CPU cycles, it is an

output bus which is used to select one of 256 pages, 4K words

each, expanding the direct addressing space to 1M word. In DMA

cycles, indicated by DMA-ACK being active, it is also an output bus

except when programmed for the physical demultiplexed DMA

mode. In this case it becomes an input to receive the 8 most

significant bits of the DMA physical address for use in the BPU

function.

Information Bus

An active HIGH bi-directional time multiplexed address/data bus.

Detection/Correction

An active HIGH bi-directional bus used for detection of errors on

Bus

undefined in this case.