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PACE1750AE

Document # MICRO-2 REV G

SIGNAL DESCRIPTIONS

CLOCKS AND EXTERNAL REQUESTS

Mnemonic

Name

Description

CPU CLK

CPU clock

A single phase input clock signal (0-40 MHz, 40 percent to 60 percent duty

cycle.

TIMER CLK

Timer clock

A 100 KHz input that, after synchronization with CPU CLK, provides the

clock for timer A and timer B. If timers are used, the CPU CLK signal

frequency must be > 300 KHz.

RESET

Reset

An active low input that initializes the device.

CON REQ

Console request

An active low input that initiates console operations after completion of the

current instruction.

INTERRUPT INPUTS

Mnemonic

Name

Description

PWRDN INT

Power down interrupt

An interrupt request input that cannot be masked or disabled. This signal

is active on the positive going edge or the high level, according to the

interrupt mode bit in the configuration register.

User interrupt

Interrupt request input signals that are active on the positive going edge

edge or the high level, according to the interrupt mode bit in the configuration

register.

I/O level interrupts

Active high interrupt request inputs that can be used to expand the number

of user interrupts.

IOL2INT

FAULTS

Mnemonic

Name

Description

MEM PRT ER

Memory protect error

An active low input generated by the MMU or BPU, or both and sampled

by the

BUS BUSY signal into the Fault Register (bit 0 CPU bus cycle, bit

1 if non-CPU bus cycle).

MEM PAR ER

Memory parity error

An active low input sampled by the

BUS BUSY signal into bit 2 of the fault

register.

EXT ADR ER

External address error

An active low input sampled by the

BUS BUSY signal into the Fault register

(bit 5 or 8), depending on the cycle (memory or I/O).

ERROR CONTROL

Mnemonic

Name

Description

UNRCV ER

Unrecoverable error

An active high output that indicates the occurrence of an error classified as

unrecoverable.

MAJ ER

Major error

An active high output that indicates the occurrence of an error classified as

major.