Page 2 of 25

PACE1750AE

Document # MICRO-2 REV G

DIFFERENCES BETWEEN THE PACE1750A AND PACE1750AE

The PACE1750AE achieves a 41% boost in performance (in clock cycles) over the PACE1750A. This reduction in clocks

per instruction is because of three architectural enhancements:

1) The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.

2) A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU’s

peripheral chips).

3) Branch calculation logic.

The table below shows how the MAC improves all multiply operations — both integer and floating point — by 477% to

760%.

PACE1750AE

PACE1750A

Instruction

Clocks

Execution

Clocks

Execution

Gain

Time (40 MHz)

Time (40 MHz) #Clocks (%)

Integer Add/Sub

4

100ns

4

100ns

—

Double Precision Integer Add/Sub

6

150ns

9

225ns

50

Integer Multiply

4

100ns

23

575ns

575

Double Precision Integer Add/Sub

9

225ns

69

1725ns

760

Floating Add/Sub

18

450ns

28

700ns

55

Extended Floating Add/Sub

34

850ns

51

1225ns

50

Floating Multiply

9

225ns

43

1075ns

477

Extended Floating Point Multiply

17

425ns

96

2400ns

564

Branch (Taken)

8

200ns

12

300ns

50

Branch (Not Taken)

4

100ns

4

100ns

—

Flt’g’ Point Polynomial Step (Mul+Add/Sub)

27

675ns

71

1775ns

263

Ext Flt’g’ Point Polynomial Step (Mul/Sub)

51

1275ns

147

3675ns

2400

DAIS Mix (MIPS)

—

3.56

—

2.52

41/59

PACE1750AE BUILT IN FUNCTIONS

A core set of additional instructions have been included in the PACE1750AE. These instructions utilize the Built ln Function

(BlF) opcode space. The objective of these new opcodes is to enhance the performance of the PACE in critical application

areas such as navigation, DSP, transcendentals and other LINPAK and matrix type instructions. Below is a list of the BlFs

and their execution times (N = the number of elements in the vector being processed).

Address

Number of

Instruction

Mnemonic

Mode

Clocks

Notes

Memory Parametric Dot Product—Single

VDPS

4F3(RA)

10 + 8 • N

Interruptable

Memory Parametric Dot Product—Double

VDPD

4F1(RA)

10+16 • N

Interruptable

3 x 3 Register Dot Product

R3DP

4F03

6

Double Precision Multiply Accumulate

MACD

4F02

8

Polynomial

POLY

4F06

7 • N - 2

Clear Accumulator

CLAC

4F00

4

Store Accumulator (32-Bit)

STA

4F08

7

Store Accumulator (48-Bit)

STAL

4F04

11

Load Accumulator (32-Bit)

LAC

4F05

9

Load Accumulator Long (48-Bit)

LACL

4F07

9

Move MMU Page Block

MMPG

4F0F

16+8 • N

Privileged

Load Timer A Reset Register

LTAR

4F0D

4

Load Timer B Reset Register

LTBR

4F0E

4