WM8804 datasheet(28/66 Pages) WOLFSON

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WM8804

Production Data

PD Rev 4.1 September 2007

The specified f2 frequencies that must be configured using the PLL_N and PLL_K register values for

reception of specific S/PDIF sample rates are as follows:

•

Mode 1 (176.4/192kHz sample rate): f2 = 98.304MHz

•

Modes 2/3/4 (32/44.1/48/88.2/96kHz sample rates): f2 = 94.3104MHz

The FREQMODE[1:0] bits are automatically controlled by the S/PDIF receiver when the receiver is

enabled and do not need to be configured in any particular initial state by the user before the S/PDIF

receiver is enabled.

Refer to Table 27 and Table 28 for details of MCLKDIV and CLKOUTDIV configuration when the

S/PDIF receiver is enabled.

The PLL register settings are configured by default to allow 32/44.1/48/88.2/96kHz (modes 2/3/4)

sample rate S/PDIF receiver operation using a 12MHz crystal clock. The PLL register settings must

be updated if:

•

Any crystal clock frequency other than 12MHz is used.

•

A S/PDIF stream with 192kHz sample rate (mode 1) is detected.

In either case, reprogramming of the PLL_N and PLL_K values (and the PRESCALE value,

depending on the crystal frequency) is necessary.

Refer to Table 31 for details of a number of recommended PLL configurations. Many other

configurations are possible; please refer to PLL Configuration section for details regarding how to

calculate alternative settings.

OSC

CLK

(MHz)

PRE-

SCALE

S/PDIF RECEIVER

SAMPLE RATE(S)

(kHz)

(MHz)

PLL_N

(Hex)

PLL_K

(Hex)

COMMENT

11.2896

32 / 44.1 / 48 / 88.2 / 96

11.2896 94.3104 8.3537

16A3B3

Set N, K

11.2896

192

11.2896 98.304 8.7075

2D4766

Set N, K

32 / 44.1 / 48 / 88.2 / 96

94.3104 7.8592

36FD21

Default Setting

192

98.304

8.192

C49BA

Set N, K

12.288

32 / 44.1 / 48 / 88.2 / 96

12.288 94.3104 7.675

2B3333

Set K

12.288

192

12.288

98.304

Set N, K

19.2

32 / 44.1 / 48 / 88.2 / 96

9.6

94.3104 9.824

346C6A

Set Prescale, N, K

19.2

192

9.6

98.304

10.24

F5C28

Set Prescale, N, K

32 / 44.1 / 48 / 88.2 / 96

94.3104 7.8592

36FD21

Set Prescale

192

98.304

8.192

C49BA

Set Prescale, N, K

32 / 44.1 / 48 / 88.2 / 96

13.5

94.3104 6.986

3F19E5

Set Prescale, N, K

192

13.5

98.304 7.2818

1208A5

Set Prescale, K

Table 31 S/PDIF Receive Mode PLL Initial Configuration Examples

The recommended configuration sequences are as follows:

TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP:

Write appropriate calculated values (relative to oscillator frequency) to PRESCALE,

PLL_N and PLL_K registers for 32/44.1/48/88.2/96kHz (modes 2/3/4) S/PDIF

receiver sample rate operation.

Enable PLL by clearing PLLPD bit.

Enable S/PDIF receiver by clearing SPDIFRXPD bit.

Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF

sample frequency and clocking mode.

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