PXAS33KBBE datasheet(19/52 Pages) PHILIPS

19 / 52 page

Philips Semiconductors

Preliminary specification

XA-S3

XA 16-bit microcontroller

32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),

I2C, 2 UARTs, 16 MB address range

2000 Dec 01

CR0, CR1, and CR2, the Clock Rate Bits

These three bits determine the serial clock frequency when the I2C

interface is in a master mode. An I2C rate of 100kHz or lower is

typical and can be derived from many oscillator frequencies. The

various serial rates are shown in Table 4. A variable bit rate may

also be used if Timer 1 is not required for any other purpose while

the I2C hardware is in a master mode. The frequencies shown in

Table 4 are unimportant when the I2C hardware is in a slave mode.

In the slave modes, the hardware will automatically synchronize with

the incoming clock frequency.

The I2C Status Register, I2STA

I2STA is an 8-bit read-only special function register. The three least

significant bits are always zero. The five most significant bits contain

the status code. There are 26 possible status codes. When I2STA

contains F8H, no relevant state information is available and no serial

interrupt is requested. All other I2STA values correspond to defined

hardware interface states. When each of these states is entered, a

serial interrupt is requested (SI = “1”).

NOTE: A detailed I2C interface description and usage

information, including example driver code, will be provided in

a separate document.

Table 4. I2C Rate Control

Frequency Select

Clock Divisor

Example I2C Rates at Specific Oscillator Frequencies

(CR2, CR1, CR0)

Clock Divisor

8 MHz

12 MHz

16 MHz

20 MHz

24 MHz

30 MHz

0h (0000)

(400)1

–

1h (0001)

(200)1

(300)1

(400)1

–

2h (0010)

(116.65)1

(176.46)1

(235.29)1

(294.12)1

(352.94)1

–

3h (0011)

90.91

(136.36)1

(181.82)1

(227.27)1

(272.73)1

(340.91)1

4h (0100)

160

100

(125)1

(150)1

(187.5)1

5h (0101)

272

29.41

44.12

58.82

73.53

88.24

(110.29)1

6h (0110)

352

22.73

34.09

45.45

56.82

68.18

85.23

7h (0111)

(Timer 1)2

NOTES:

1. The XA-S3 I2C interface does not conform to the 400kHz I2C specification (which applies to rates greater than 100kHz) in all details, but

may be used with care where higher rates are required by the application.

2. The timer 1 overflow is used to clock the I2C interface. The resulting bit rate is 1/2 of the timer overflow rate.

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