数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

CS8421 数据表(PDF) 13 Page - Cirrus Logic

部件名 CS8421
功能描述  32-bit, 192 kHz Asynchronous Sample Rate Converter
PDF  38 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS8421 数据表(HTML) 13 Page - Cirrus Logic

Back Button CS8421 Datasheet HTML 9Page - Cirrus Logic CS8421 Datasheet HTML 10Page - Cirrus Logic CS8421 Datasheet HTML 11Page - Cirrus Logic CS8421 Datasheet HTML 12Page - Cirrus Logic CS8421 Datasheet HTML 13Page - Cirrus Logic CS8421 Datasheet HTML 14Page - Cirrus Logic CS8421 Datasheet HTML 15Page - Cirrus Logic CS8421 Datasheet HTML 16Page - Cirrus Logic CS8421 Datasheet HTML 17Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 38 page
background image
DS641F1
13
CS8421
DIGITAL INPUT CHARACTERISTICS
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
SWITCHING SPECIFICATIONS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameters
Symbol
Min
Typ
Max
Units
Input Leakage Current
Iin
--
±10
µA
Input Capacitance
Iin
-8
-
pF
Input Hysteresis
-250
-
mV
Parameters
Symbol
Min
Max
Units
High-Level Output Voltage, except MCLK_OUT and SDOUT (IOH=-4 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, except MCLK_OUT and SDOUT (IOL=4 mA)
VOL
-.6
V
High-Level Output Voltage, MCLK_OUT
(IOH=-6 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, MCLK_OUT
(IOL=6 mA)
VOL
-.6
V
High-Level Output Voltage, SDOUT
(IOH=-8 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, SDOUT
(IOL=8 mA)
VOL
-.65
V
High-Level Input Voltage
VIH
0.6xVL
VL+0.3
V
Low-Level Input Voltage
VIL
-0.3
0.8
V
Parameters
Symbol
Min
Max
Units
RST pin Low Pulse Width
(Note 6)
1-
ms
XTI Frequency (Note 7)
Crystal
Digital Clock Source
16.384
1.024
27.000
27.000
MHz
MHz
XTI Pulse Width High/Low
14.8
-
ns
MCLK_OUT Duty Cycle
45
55
%
Slave Mode
I/OSCLK Frequency
-
24.576
MHz
OLRCK High Time
(Note 8)
tlrckh
326
-
ns
I/OSCLK High Time
tsckh
9-
ns
I/OSCLK Low Time
tsckl
9-
ns
I/OLRCK Edge to I/OSCLK Rising
tlcks
6-
ns
OLRCK Rising Edge to OSCLK Rising Edge (TDM)
tfss
5-
ns
I/OSCLK Rising Edge to I/OLRCK Edge
tlckd
5-
ns
OSCLK Rising Edge to OLRCK Falling Edge (TDM)
tfsh
5-
ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid
tdpd
-18
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
3.5
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
5-
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com