CS42438 datasheet(31/62 Pages) CIRRUS

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DS646F1

CS42438

No Power

1. VQ = ?

2. Aout bias = ?

3. No audio signal

generated.

Control Port

Accessed

Control Port

Access Detected?

Valid MCLK

Applied?

Valid MCLK

Applied?

PDN bit = '1'b?

Sub-Clocks Applied

1. LRCK valid.

2. SCLK valid.

3. Audio samples

processed.

Valid

MCLK/LRCK

Ratio?

Yes

Normal Operation

1. VQ = VA/2.

2. Aout bias = VA/2.

3. Audio signal generated per register settings.

Analog Output Freeze

1. VQ = VA/2.

2. Aout bias = VA/2 + last audio sample.

3. No audio signal generated.

Analog Output Mute

1. VQ = VA/2.

2. Aout bias = VA/2.

3. No audio signal generated.

ERROR: MCLK/LRCK ratio change

ERROR: MCLK removed

RST = Low

ERROR: Power removed

PDN bit set

to '1'b

Software Mode

Registers setup to

desired settings.

Hardware Mode

H/W pins setup to

desired settings.

RST = Low?

2000 LRCK delay

Power-Up

1. VQ = VA/2.

2. Aout bias = VQ.

Power-Down

1. VQ discharge to 0 V.

2. Aout bias = Hi-Z.

3. No audio signal generated.

4. Control Port Registers retain

settings.

Power-Down (Power Applied)

1. VQ = 0 V.

2. Aout = Hi-Z.

3. No audio signal generated.

4. Control Port Registers reset

to default.

Figure 11. Audio Output Initialization Flow Chart

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