ICS9DB102

2 Output Express* Buffer with CLKREQ# Function

ICS9DB102

REV F

08/06/07

2 Output PCI Express* Buffer with CLKREQ# Function

DATASHEET

1

SPREAD

COMPATIBLE

PLL

CONTROL

LOGIC

SMBDAT

SMBCLK

CLK_INT

C LK_IN C

PLL_BW

IREF

PCIEX0

PCIEX1

CLKREQ1#

CLKREQ0#

Description

Output Features

1-to-2 Zero-delay or fanout buffer for PCI Express.The

ICS9DB102 zero-delay buffer supports PCI Express clocking

requirements. The ICS9DB102 is driven by a differential SRC

output pair from an ICS CK409/CK410-compliant main clock

generator such as the ICS952601 or ICS954101. It attenuates

jitter on the input clock and has a selectable PLL Band Width to

maximize performance in systems with or without Spread-

Spectrum clocking.

•

2 - 0.7V current mode differential output pairs (HSCL)

Funtional Block Diagram

Key Specifications

•

Cycle-to-cycle jitter < 35ps

•

Output-to-output skew < 25ps

Features/Benefits

•

CLKREQ# pin for outputs 1 and 4/output enable for Express

Card applications

•

PLL or bypass mode/PLL can dejitter incoming clock

•

Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL’s

•

Spread Spectrum Compatible/tracks spreading input clock

for low EMI

•

SMBus Interface/unused outputs can be disabled