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ICS952906A 数据表(PDF) 11 Page - Integrated Circuit Systems

部件名 ICS952906A
功能描述  Programmable Timing Control Hub for Next Gen P4??processor
PDF  23 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS952906A 数据表(HTML) 11 Page - Integrated Circuit Systems

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11
Integrated
Circuit
Systems, Inc.
ICS952906A
1236A—08/06/07
I
2C Table: Vendor & Revision ID Register
Control
Function
Bit 7
RID3
R
X
Bit 6
RID2
R
X
Bit 5
RID1
R
X
Bit 4
RID0
R
X
Bit 3
VID3
R
0
Bit 2
VID2
R
0
Bit 1
VID1
R
0
Bit 0
VID0
R
1
I
2C Table: Byte Count Register
Control
Function
Bit 7
BC7
RW
0
Bit 6
BC6
RW
0
Bit 5
BC5
RW
0
Bit 4
BC4
RW
0
Bit 3
BC3
RW
1
Bit 2
BC2
RW
1
Bit 1
BC1
RW
1
Bit 0
BC0
RW
1
I
2C Table: Watchdog Timer Register
Control
Function
Bit 7
WD7
WD Timer Bit 7
RW
0
Bit 6
WD6
WD Timer Bit 6
RW
0
Bit 5
WD5
WD Timer Bit 5
RW
0
Bit 4
WD4
WD Timer Bit 4
RW
0
Bit 3
WD3
WD Timer Bit 3
RW
1
Bit 2
WD2
WD Timer Bit 2
RW
0
Bit 1
WD1
WD Timer Bit 1
RW
1
Bit 0
WD0
WD Timer Bit 0
RW
1
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Bit 7
M/NEN
M/N Programming
Enable
RW
0
Bit 6
WDEN
Watchdog Enable
R
0
Bit 5
WDFSEN
WD Safe Frequency
Mode
RW
0
Bit 4
WD SF4
RW
0
Bit 3
WD SF3
RW
0
Bit 2
WD SF2
RW
0
Bit 1
WD SF1
RW
0
Bit 0
WD SF0
RW
0
--
1
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
0
--
--
--
--
1
--
--
--
PWD
01
Disable
Enable
01
Byte 9
Pin #
Name
Type
Disable
Enable
Latched FS/Byte0
These bits represent X*290ms the
watchdog timer waits before it goes to
alarm mode. Default is 11 x 293ms =
3.2s.
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
WD B10 b(4:0)
-
Watch Dog Safe Freq
Programming bits
-
-
-
-
-
-
PWD
-
Byte 10
Pin #
Name
Type
-
-
-
-
-
PWD
-
Byte Count
Programming b(7:0)
-
-
-
-
-
-
-
Type
-
Type
-
VENDOR ID
-
-
Name
Byte 8
Pin #
PWD
-
REVISION ID
-
-
-
Byte 7
Pin #
Name
0
-
-
-



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