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ICS952906A 数据表(PDF) 9 Page - Integrated Circuit Systems |
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ICS952906A 数据表(HTML) 9 Page - Integrated Circuit Systems |
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9 / 23 page ![]() 9 Integrated Circuit Systems, Inc. ICS952906A 1236A—08/06/07 I 2C Table: Frequency Select Register Control Function Bit 7 FS Source Frequency H/W IIC Select RW 0 Bit 6 FS6 Freq Select Bit 6 RW 0 Bit 5 FS5 Freq Select Bit 5 RW 0 Bit 4 FS4 Freq Select Bit 4 RW 0 Bit 3 FS3 Freq Select Bit 3 RW 0 Bit 2 FS2 Freq Select Bit 2 RW 0 Bit 1 FS1 Freq Select Bit 1 RW 0 Bit 0 FS0 Freq Select Bit 0 RW 0 I 2C Table: Spreading and Device Behavior Control Register Control Function Bit 7 SS1 Spread Select 1** RW 0 Bit 6 SS0 Spread Select 0** RW 1 Bit 5 SS_EN Spread Enable Control RW 1 Bit 4 WDS_EN WD Soft Reset Enable RW 0 Bit 3 Reserved Reserved RW 1 Bit 2 CPUCLKT/C_ITP, CPU1T/C, CPU0T/C Output Control RW 1 Bit 1 CPUCLKT/C_1 Output Control RW 1 Bit 0 CPUCLKT/C_0 Output Control RW 1 I 2C Table: Output Control Register Control Function Bit 7 25MHz_0 Output Control RW 1 Bit 6 25MHz_1 Output Control RW 1 Bit 5 CPUT Stop Mode 0: CPUT Driven during PD#; 1: Tri-stated RW 0 Bit 4 Reserved Reserved RW 1 Bit 3 3V66_1 Output Control RW 1 Bit 2 Reserved Reserved RW 1 Bit 1 CPUCLKT/C_1 Output Stop Control RW 1 Bit 0 CPUCLKT/C_0 Output Stop Control RW 1 I 2C Table: Output Control Register Control Function Bit 7 ASEL1 3V66/PCI Freq Select RW 0 Bit 6 PCICLK6 Output Control RW 1 Bit 5 PCICLK5 Output Control RW 1 Bit 4 PCICLK4 Output Control RW 1 Bit 3 PCICLK3 Output Control RW 1 Bit 2 PCICLK2 Output Control RW 1 Bit 1 PCICLK1 Output Control RW 1 Bit 0 PCICLK0 Output Control RW 1 Disable Enable See Table 5: Async AGP/PCI Freq Table Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Free Run Stoppable Disable Enable -- Free Run Stoppable Disable Enable Disable Enable -- Disable Enable Driven Hi-Z Disable Enable Disable Disable Enable Enable ON OFF -- 01 = 0.25% Reserved PWD - Byte 3 Pin # Name Type 0 1 36 35 26 - 42,41 39, 38 20 Type PWD 39, 38 Byte 2 Pin # Name 0 1 ** Spread program m ing only applies for ROM table entries 0001000 to 0001011 and 0010000 to 0010111 - - 45, 44 42,41 ON OFF - PWD - - Byte 1 Pin # Name Type 00 = 0.20% 10 = 0.35% - - See Table 1: QuadRom Frequency Selection Table 01 PWD - Byte 0 Pin # Name Type Latch Inputs IIC 01 - - - - - 19 16 15 14 13 12 - - |
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