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P4C1023L-55CWC 数据表(PDF) 4 Page - Pyramid Semiconductor Corporation

部件名 P4C1023L-55CWC
功能描述  LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM
PDF  11 Pages
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制造商  PYRAMID [Pyramid Semiconductor Corporation]
网页  http://www.pyramidsemiconductor.com
标志 PYRAMID - Pyramid Semiconductor Corporation

P4C1023L-55CWC 数据表(HTML) 4 Page - Pyramid Semiconductor Corporation

  P4C1023L-55CWC Datasheet HTML 1Page - Pyramid Semiconductor Corporation P4C1023L-55CWC Datasheet HTML 2Page - Pyramid Semiconductor Corporation P4C1023L-55CWC Datasheet HTML 3Page - Pyramid Semiconductor Corporation P4C1023L-55CWC Datasheet HTML 4Page - Pyramid Semiconductor Corporation P4C1023L-55CWC Datasheet HTML 5Page - Pyramid Semiconductor Corporation P4C1023L-55CWC Datasheet HTML 6Page - Pyramid Semiconductor Corporation P4C1023L-55CWC Datasheet HTML 7Page - Pyramid Semiconductor Corporation P4C1023L-55CWC Datasheet HTML 8Page - Pyramid Semiconductor Corporation P4C1023L-55CWC Datasheet HTML 9Page - Pyramid Semiconductor Corporation Next Button
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P4C1023/P4C1023L
Page 4 of 11
Document # SRAM126 REV OR
Notes:
1. WE is HIGH for READ cycle.
2. CE and OE are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE transition LOW.
READ CYCLE NO. 1 (OE
OE
OE
OE
OE CONTROLLED)(1)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE
CE
CE
CE
CE CONTROLLED)
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.



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