83023AMI

www.icst.com/products/hiperclocks.html

REV. B JANUARY 18, 2006

7

Integrated

Circuit

Systems, Inc.

ICS83023I

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The

ratio of R1 and R2 might need to be adjusted to position the

V_REF in the center of the input voltage swing. For example, if

the input clock swing is only 2.5V and V

be 1.25V and R2/R1 = 0.609.

V_REF

R1

1K

C1

0.1u

R2

1K

Single Ended Clock Input

CLK

nCLK

VDD

For applications not requiring the use of the differential input,

both CLK and nCLK can be left floating. Though not required,

but for additional protection, a 1k

Ω resistor can be tied from

CLK to ground.

All unused LVCMOS output can be left floating. We

recommend that there is no trace attached.

ICS83023I

DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER

TSD

IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER

ICS83023I

7