PM7366-PI datasheet(92/286 Pages) PMC

92 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

R/W

TFUDRE

Bit 14

R/W

IOCE

Bit 13

R/W

TDFQEE

Bit 12

R/W

TDQRDYE

Bit 11

R/W

TDQFE

Bit 10

R/W

RPDRQEE

Bit 9

R/W

RPDFQEE

Bit 8

R/W

RPQRDYE

Bit 7

R/W

RPQLFE

Bit 6

R/W

RPQSFE

Bit 5

R/W

RFOVRE

Bit 4

R/W

RPFEE

Bit 3

R/W

RABRTE

Bit 2

R/W

RFCSEE

Bit 1

R/W

PERRE

Bit 0

R/W

SERRE

This register provides interrupt enables for various events detected or initiated by the FREEDM.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

SERRE:

The system error interrupt enable bit (SERRE) enables PCI system error interrupts to the PCI

host. When SERRE is set high, any address parity error, data parity error on Special Cycle

commands, reception of a master abort or detection of a target abort will cause an interrupt to

be generated on the PCIINTB output. Interrupts are masked when SERRE is set low.

PM7366-PI 数据表(PDF) 92 Page - PMC-Sierra, Inc

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