PM7366-PI datasheet(96/286 Pages) PMC

96 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

TFUDRI

Bit 14

IOCI

Bit 13

TDFQEI

Bit 12

TDQRDYI

Bit 11

TDQFI

Bit 10

RPDRQEI

Bit 9

RPDFQEI

Bit 8

RPQRDYI

Bit 7

RPQLFI

Bit 6

RPQSFI

Bit 5

RFOVRI

Bit 4

RPFEI

Bit 3

RABRTI

Bit 2

RFCSEI

Bit 1

PERRI

Bit 0

SERRI

This register reports the interrupt status for various events detected or initiated by the FREEDM.

Reading this registers acknowledges and clears the interrupts.

Note

This register is not byte addressable. Reading this register clears all the interrupt bits in the

when all four byte enables are negated, no access is made to this register.

SERRI:

The system error interrupt status bit (SERRI) reports PCI system error interrupts to the PCI

host. SERRI is set high upon detection of any address parity error, data parity error on

Special Cycle commands, reception of a master abort or detection of a target abort event.

PM7366-PI 数据表(PDF) 96 Page - PMC-Sierra, Inc

PM7366-PI 数据表(HTML) 96 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载