PTH12030LAH datasheet(3/26 Pages) TI

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ELECTRICAL CHARACTERISTICS

PTH12030W/L

SLTS211F – MAY 2003 – REVISED FEBRUARY 2007

A = 25°C, VI = 12 V, VO = 3.3 V, CI = 560 µF, CO = 0 µF, and IO = IOmax (unless otherwise stated)

PTH12030W

CHARACTERISTICS

CONDITIONS

MIN

TYP

MAX

UNIT

°C, 200 LFM airflow

26(1)

Output current

°C, natural convection

26(1)

Input voltage range

Over lO range

10.2

13.8

VO tol

Set-point voltage tolerance

±2(2)

%VO

∆Regtemp

Temperature variation

–40

°C < T

A < 85°C

±0.5

%VO

∆Regline

Line regulation

Over VI range

±5

∆Regload

Load regulation

Over IO range

±5

∆Regtot

Total qutput variation

Includes set-point, line, load, –40

°C ≤ T

A ≤ 85 °C

±3(2)

%VO

∆Vadj

VO adjust range

Over VI range

1.2

5.5

RSET = 280 Ω

VO = 5 V

94.5%

RSET = 2 kΩ

VO = 3.3 V

92.7%

RSET = 4.32 kΩ

VO = 2.5 V

91.4%

Efficiency

IO = 18 A

RSET = 11.5 kΩ

VO = 1.8 V

89.5%

RSET = 24.3 kΩ

VO = 1.5 V

88.2%

RSET = open circuit VO = 1.2 V

86.2%

VO ripple (peak-to-peak)

20-MHz bandwidth

All Voltages

mVPP

IO trip

Overcurrent threshold

Reset, followed by auto-recovery

ttr

Recovery Time

µS

1 A/

µs load step,

Transient response

50 to 100% IOmax, CO= 330 µF

∆Vtr

VO over/undershoot

150

Margin up/down adjust

±5%

Margin control (pins 12&13)

Margin input current, Pin to GND

-8(3)

µA

IIL track

Track input current (pin 11)

Pin to GND

-0.13(4)

µA

dVtrack/dt

Track slew rate capability

CO≤ CO(max)

V/ms

VI increasing

9.5

UVLO

Undervoltage lockout

VI decreasing

8.8

8.5

Input high voltage (VIH)

Referenced to GND

2.5

Open(5)

Inhibit

control

Input low voltage (VIL)

Referenced to GND

–0.2

0.5

(pin 4)

Input low current (IIL)

Pin 4 to GND

0.5

µA

II inh

Input standby current

Inhibit (pin 4) to GND, track (pin 11) VI

Switching frequency

Over VI and IO ranges

475

575

675

kHz

External input capacitance

560(6)

µF

nonceramic

330(7) 7,150(8)

Capacitance value

µF

External output capacitance

ceramic

300

Equiv. series resistance (nonceramic)

4(9)

Ω

MTBF

Reliability

Bellcore TR-332, 50% stress, TA=40°C, ground benign

106 Hrs

(1)

See SOA curves or consult factory for appropriate derating.

(2)

The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a

tolerance of 1 %, with 100 ppm/

°C (or better) temperature stability.

(3)

A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.

(4)

A low-leakage (<100 nA), open-drain device, such as MOSFET or voltage supervisor IC, is recommended to control this pin.

(5)

This control pin is pulled up to an internal 5-V source. To avoid risk of damage to the module, do not apply an external voltage greater

than 7 V. If it is left open-circuit, the module operates when input power is applied. A small, low-leakage (<100 nA) MOSFET or

open-drain/collector voltage supervisor IC is recommended for control. For further info, see the related application information section.

(6)

A 560

µF electrolytic input capacitor, rated for a minimum of 500 mArms of ripple current is required for proper operation.

(7)

An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load will improve the

transient response.

(8)

This is the calculated maximum. The minimum ESR limitation often results in a lower value. See the application information section.

(9)

This is the typical ESR for all the electrolytic (nonceramic) ouput capacitance. Use 7 m

Ω as the minimum when using max-ESR values

to calculate.

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